Design of a digital carrier generator

I wish to design a digital carrier generator, the diagram of which i am attaching herein..for the same i have used the following building blocks:

1> 2:1 Mux(multibit)
2> Digital Integrator (multibit)
3> A Delta function block (unit impulse function)
4> A Clock
5> A 4x4 bit multiplier, wherein only the first 4 bits of the product have been considered.

I ran the code and it synthesized perfectly well..but on generation of test bench waveform, the output ports were undefined..

i m unable to figure out as to how to supply the values to the building blocks through the signals...

Please suggest the required changes/errors..

The codes for each building block has been attached below.

Thanks.

CODES:

1> CARRIER GENERATOR

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY carrier_gen IS
GENERIC (
WIDTH : INTEGER := 4
);
PORT (
y : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
x : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0)

);
END carrier_gen;

ARCHITECTURE trans OF carrier_gen IS

SIGNAL a : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
SIGNAL c : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
SIGNAL del : STD_LOGIC;
SIGNAL clock : STD_LOGIC;

-- Declare intermediate signals for referenced outputs
SIGNAL y_xhdl0 : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);



Component mux_2to1 IS
GENERIC (
WIDTH : INTEGER := 4
);
PORT (
c : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
a : IN STD_LOGIC;
sel : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0)
);
END component;

component dig_int IS
GENERIC (
WIDTH : INTEGER := 4
);
PORT (
y : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
x : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
clock : IN STD_LOGIC
);
END component;

component multiply is
PORT (
prod : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;

component delta IS
PORT (
del : OUT STD_LOGIC
);
END component;

component clk_gen is
port(clockut std_logic);
end component;

BEGIN
-- Drive referenced outputs

y <= y_xhdl0;
m1 : mux_2to1 PORT MAP (c,del,del,b);

d1 : dig_int PORT MAP (a,c,clock);

d2 : dig_int PORT MAP (y_xhdl0,a,clock);

m2 : multiply PORT MAP (b,y_xhdl0,x);

d3 : delta PORT MAP (del);

c2 : clk_gen PORT MAP (clock);

END trans;

2>CLOCK

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_gen is
port(clockut std_logic);
end clk_gen;

architecture Behavioral of clk_gen is


-- Declare intermediate signals for referenced outputs
SIGNAL clock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
clock <= clock_xhdl0;

PROCESS
BEGIN
for i in 1 to 10 loop

clock_xhdl0 <= '1';

wait for 100 ns;
clock_xhdl0 <= NOT(clock_xhdl0);
wait for 100 ns;
end loop;
END PROCESS;

end Behavioral;

3>Delta


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY delta IS
PORT (
del : OUT STD_LOGIC
);
END delta;

ARCHITECTURE trans OF delta IS
BEGIN

PROCESS
BEGIN
WAIT FOR 0 ns;
del <= '1';
WAIT FOR 100 ns;
del <= '0';
WAIT;
END PROCESS;


END trans;

4>Integrator



LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY dig_int IS
GENERIC (
WIDTH : INTEGER := 4
);
PORT (
y : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
x : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
clock : IN STD_LOGIC
);
END dig_int;

ARCHITECTURE trans OF dig_int IS
SIGNAL z : STD_LOGIC_vector(WIDTH - 1 downto 0):="0000";

-- Declare intermediate signals for referenced outputs
SIGNAL y_xhdl0 : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
BEGIN
-- Drive referenced outputs
y <= y_xhdl0;

PROCESS (x, z)
BEGIN
y_xhdl0 <= x + z;
END PROCESS;


PROCESS (clock)
BEGIN
IF (clock'EVENT AND clock = '1') THEN
z <= y_xhdl0;
END IF;
END PROCESS;


END trans;

5>Multiplier

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiply is


PORT (
prod : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end multiply;

architecture Behavioral of multiply is
constant n:integer :=4;
subtype plary is std_logic_vector(n-1 downto 0);
type pary is array(0 to n) of plary;
signal pp,pc,psary;
begin
pgen:for j in 0 to n-1 generate
pgen1:for k in 0 to n-1 generate
pp(j)(k)<=a(k) and b(j);
end generate;
pc(0)(j)<='0';
end generate;
ps(0)<=pp(0);
prod(0)<=pp(0)(0);
addr:for j in 1 to n-1 generate
addc:for k in 0 to n-2 generate
ps(j)(k)<=pp(j)(k) xor pc(j-1)(k) xor ps(j-1)(k+1);
pc(j)(k)<=(pp(j)(k) and pc(j-1)(k)) or
(pp(j)(k) and ps(j-1)(k+1)) or
(pc(j-1)(k)and ps(j-1)(k+1));
end generate;
prod(j)<=ps(j)(0);
ps(j)(n-1)<=pp(j)(n-1);
end generate;

end Behavioral;

6> 2:1 MUX




LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY mux_2to1 IS
GENERIC (
WIDTH : INTEGER := 4
);
PORT (
c : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
a : IN STD_LOGIC;
sel : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0)
);
END mux_2to1;

ARCHITECTURE trans OF mux_2to1 IS
BEGIN

c <= ("000" & a) WHEN (sel = '1') ELSE
b;

END trans;

Is it a VLSI design process? sorry I do not know anything about VLSI designig process. I think you edit your post and mention the name of the software you are using. Then you will may get many answers.

ahsan_eda said:

Is it a VLSI design process? sorry I do not know anything about VLSI designig process. I think you edit your post and mention the name of the software you are using. Then you will may get many answers.

Click to expand...

I m working on Xilinx 9.2i ISE to implement thefollowing process..no it aint a VLSI process..

I am trying to implement this on Xilinx 9.2i ISE...

I am unable to update the 4-bit signals(a,b and c) which are used interchangeably as input and output in the connecting blocks.
Eg. The signal c which is the output of mux is also the input of the 1st integrator. Since the values are not being updated, as a result the signals are showing as undefined in the tbw simulation.

Please help me identify and rectify the error.