does someone know the trend in low-power technics field?

i want to study in low-power field, and may concern about the gated-clk design, low-power clock network and voltage scaling,does someone knows the trend in low-power design technics ?Thanks

Here is one paper that publish in 1995 for your reference.

thanks first

But I want to know now the trend in 2001 and 2002

This book may help :
**broken link removed**
But I don't have it ...

There are many trends exhibited by some research groups:

1. multiple or variable voltage supplies (transistor-level)

2. application transformations that infer differentiations at the system level
e.g. the memory subsystem organization and the update rules for these memories. (RTL and system level)

3. adiabatic switching (transistor level)

4. operation of MOS transistors at the SUBTHRESHOLD REGION. Where the current-law is exponential.
Operating current at the subthreshold are in the region of: few pA- few nA which are 2-5 orders
of magnitude lower than saturation or linear region.

5. Quantum electronics (single-electron transistors)

6. Novel clocking, clock distribution, power-down and other techniques.

Which one dominates, it's extremely hard to tell.

the_penetrator©