sonika tanwani
Newbie level 4
Hello all,
I am designing a PCI-FPGA board with PLX 9052 as the PCI compliant agent. The outputs that i m taking from PLX are local address n data bus with 5V/8mA capability and write signal with 5V/12mA drive strength. All these signals have been pulled up using 10K resistors. These outputs are level translated by means of QS3861 bus switches to 3.3V at the input of XC3S400 spartan3 FPGA. When I saw the IBIS model of FPGA in XilinxISE, I found that it has described the signals as LVCMOS25_F_12mA. for all signals. ie. it has taken 12mA drive current for all IOs by default and 2.5V LVCMOS signalling standars. I have set 3.3V on bank 4 thus my signalling standard is 3.3V but what is the current that i m getting?I want to know that what is the exact condition or is it by default set to that value. How can we edit the default settings or attributes of FPGA?
Kindly help me in this regard.
Also if there are any suggestions regarding the design considerations for reliability of FPGA design and VHDL code, it will be welcome. Pls reply as soon as possible.
Regards,
Sonika
I am designing a PCI-FPGA board with PLX 9052 as the PCI compliant agent. The outputs that i m taking from PLX are local address n data bus with 5V/8mA capability and write signal with 5V/12mA drive strength. All these signals have been pulled up using 10K resistors. These outputs are level translated by means of QS3861 bus switches to 3.3V at the input of XC3S400 spartan3 FPGA. When I saw the IBIS model of FPGA in XilinxISE, I found that it has described the signals as LVCMOS25_F_12mA. for all signals. ie. it has taken 12mA drive current for all IOs by default and 2.5V LVCMOS signalling standars. I have set 3.3V on bank 4 thus my signalling standard is 3.3V but what is the current that i m getting?I want to know that what is the exact condition or is it by default set to that value. How can we edit the default settings or attributes of FPGA?
Kindly help me in this regard.
Also if there are any suggestions regarding the design considerations for reliability of FPGA design and VHDL code, it will be welcome. Pls reply as soon as possible.
Regards,
Sonika
