sp_sara
Junior Member level 2
Hi there,
we have an FPGA project with a Synopsys dc_shell - Xilinx ISE
design flow. There are dc_shell scripts that used to work well, but now
the command syntax has obviously changed to TCL in version B-2008.09.
That is not a problem.
But, when I try to do
write -f edif
I get the error message:
Error: format EDIF not supported in XG mode. Please contact your
Synopsys support if you need assistance. (XG-104)
How can I create an EDIF file with the new Design Compiler? Or is there
a way to use the .ddc files with Xilinx?
Thank You very much for Your advice,
we have an FPGA project with a Synopsys dc_shell - Xilinx ISE
design flow. There are dc_shell scripts that used to work well, but now
the command syntax has obviously changed to TCL in version B-2008.09.
That is not a problem.
But, when I try to do
write -f edif
I get the error message:
Error: format EDIF not supported in XG mode. Please contact your
Synopsys support if you need assistance. (XG-104)
How can I create an EDIF file with the new Design Compiler? Or is there
a way to use the .ddc files with Xilinx?
Thank You very much for Your advice,