need help loading an srec file format into verilog memory

I am trying to load an srec file into to a byte-addressable memory in Verilog

The memory has to be one megabyte and has to have a 32-bit address input

- I am running into the following issues

-according to the srec format I have to load data into specific addresses. how to map hex addresses to a Verilog memory like this one

reg [ horizontal_length: 0] memory [ vertical_Depth: 0];

Sample line from a srec file is

S30D8002004003E000080000000045

S3 means the address is 32bit in length. 0D is the total byte size making up all the characters.Following this is 8002004 which is the 32-bit address in memory where data is to be stored. Everything afterwards is the data being written at that address except the last two characters(45) which represent check. I have to parse the file in Verilog and load the data into the address being specified

Also can anyone please recommend a good source for performing Verilog file i/o since the parsing of the srec file needs file i/o

Thanks you

Dear Hasan

Well I dont have much idea about srec, Well I hope you can find sufficient help on this link www.testbench.in
Under verification concepts from verilog you may be able to get the result hope so

Good luck