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how to avoid loop unrolling in verilog synthesis

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rocking_vlsi

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Hi

Some part of my verilog code is like this.

Code:
for(i=0;i<10;i++) begin
for(j=0;j<10;j++)begin
acc<=acc+read_memory();
end
end

As of my knowledge for loop will be unrolled while synthesis. Since memory read cannot be parallel in my case... How to avoid for loop unrolling during synthesis.
 

You have to use synthesis directive to tell the synthesis tool not to compile the code. Do it as follows

Code:
// synthesis translate_off
for(i=0;i<10;i++) begin
for(j=0;j<10;j++)begin
acc<=acc+read_memory();
end
end
// synthesis translate_on
 
If i am using RTL compiler.... what would be the synthesis directive?
. Is there manual regarding this RTL compiler user guide?
 

If you want your code synthesized, and your memory cannot do reads in parallel, then you can't use a for loop to do this. Unless you are using behavioral synthesis, which is a level above RTL, you will have to schedule the reads to happen over a number of cycles.
 
Can you elaborate your answer using sample code...
 
Last edited:

If you can give me a complete example that shows the functionality you desire (and simulates without errors), I might be able to give you a sample back.
 
If your example is too big to post here, then I don't have the time to help you. Maybe someone else can.
 

Sorry Dave...
My problem is briefly explained here...

Code:
/////////////////////////////////////
reg [7:0] Image [8:0][8:0]; // image in RAM

reg [7:0] Temp_matrix [2:0][2:0];

for(every possible 3x3 matrix from Image)
{
    Image_segment[2:0][2:0]=  read_3x3_matrix_from_RAM;
    result=absolute_difference ( Image_segment[2:0][2:0],Temp_matrix[2:0][2:0]);
}
 

Did you figure out the solution to this problem?
 

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