Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Need help in I2C slave

Status
Not open for further replies.
S

sakthikumaran87

Full Member level 3
Joined
Nov 9, 2009
Messages
160
Helped
21
Reputation
42
Reaction score
21
Trophy points
1,298
Location
India
Activity points
2,176
Hi All,

I have been assigned to relise an I2C slave and i have to make it compatible with Standard, fast and HS modes. My doubt is, when coding in HDL how can we assure that they are designed as per the protocol requirements to transfer 100kbps....3.4Mbps resp. If the frequency of the design is the key then what should be the frequency of the design to be closed in STA?? what is the formula to calculate this relationship betweem Mbps and frequency. Kindly Guide.

Thanks in Advance.
 

coding in HDL how can we assure that they are designed as per the protocol requirements to transfer 100kbps....3.4Mbps resp.[/QUOTE]

I2C (even at 400kbs) is considered VERY low speed chip design. Therefore the speed limitations will come from
correct (or incorrect) PCB design - don't worry about IC timings when describing the I2C tranciever with HDL.
 

Hi Shaiko,

Thanks for your reply. Just now i had a discussion with one of my friends. He said that we can transfer a max. of 1 bit per clock cycle. so if we want to transfer 400kbits per sec then we need to close scl at 400KHz frequency to match our need. If we consider even scl as a signal in RTL and use a higher freq. clock to sample both scl and sda lines then we need to close timing atlest twice ie., 800kHz as per nyquist criterion. pl comment on this.
 

in I2C ea byte have extra bit(ACK), so if u will run @400Khz u will achieve 355,(5) Kbit per sec speed max. so for 400Kbit per sec. you need 450KHz frequency.
 

Hi Lauris,

Your claim makes sense. Thanks. Ya it should close at 450kHz. Thanks for notifying me.
 

Just one question, did your design is clock less, I mean you only used the SCL clock to handle the I2C protocol, or did you used another clock to sample the I2C lines and respect the protocol?

For info, Synopsys has some ip to test your code with all mode, standard, fast, fast+,high mode.
 

Hi, everyone.

referencing the i2c slave RTL code supported by opencores.org, internal clock frequency is 48MHz.

I don't fully understand internal operation of I2C slave. but higher frequency internal clock than external data rate seems to be needed.

internal clock samples SCA and SDA.
 

the entire i2c/sma spec is written to allow internal oversampling.

If you want to use the scl/sda lines as clocks/edge sensitives, you will need to make sure the IO are set up with the ability to rejct noise (for fast/high speed), and with the internally generated hold time (to prevent simultaneous changes in SDA/SCL from being picked up as a start condition).
 

Hi rca,

I am planning to use another clock to sample the i2c lines and respect the protocol. Can u give me some more info on Synopsys ip? Their web address?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top