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IN industry prefer VHDL or verilog?

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That depends on the field of work and geographical location.
In ASIC design VHDL is almost never used and Verilog is dominant.
With FPGA design VHDL is dominant in Europe and around 50/50 with Verilog in the US.
 
Hi,
If you know any one that is enough, the interviewer always asks which one you know (atleast it was true in my case).

Thanks,
Manoj
 

shaiko said:
In ASIC design VHDL is almost never used and Verilog is dominant.
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This has to be clarified. The netlists that are sent to the ASIC manufacturer are always Verilog, but both languages are used for the RTL design. I don't know the percentages. It is not a problem to do a VHDL or mixed VHDL/Verilog RTL design and deliver a Verilog netlist to the manufacturer.
 

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