sages
Newbie level 6
Some thought it means the delay from the signal source to the first register in the core design.
But according to <ASIC timing verification> book, it seems that it means the delay from the signal source to the first stage circuit (no matter register or gate) in the core design.
These two explanations are totally different. And which is right?
But according to <ASIC timing verification> book, it seems that it means the delay from the signal source to the first stage circuit (no matter register or gate) in the core design.
These two explanations are totally different. And which is right?
