loop stability problem of DCDC

Helllo all,
currently, I am facing a problem refer to the loop stability of DCDC; it is voltage mode and I designed the loop gain and phase margin as follows:

* it is obvious to see that phase margin is around 40 degree (at gain=0db)
* while there is a region that when gain>odb but phase margin <0, as show in picture -16 degree @ 46db

It confuse me a lot that whether the loop stable or not? or what is the "true" phase margin for this loop?
While, through a transient simulation (adding current in output fast -> load trans response), it is stable, as showing following:


can anybody help me to solve this problem whether this kind of loop stable or not? and is there any other way to judge the loop stabiliy?
thanks

It's stable. If you can rely on the constancy of filter parameters, e.g. capacitor ESR or whatever acts as a phase leading element in this case.

Depending on the real circuit details, it may be interesting to check stable recovery from larger input and load steps.

I believe in such situations, a bode plot isn't sufficient to determine stability. You need to use a nyquist plot or something similar.

There is a spurious resonance @ 9KHz with 25dB gain above normal at that point, so negative feedback becomes positive when Gain>1 & Phase Margin=0

what are the switching rates of SMPS1, SMPS2 and also Load if known.? Pre-load may be necessary as well as lower ESR caps as suggested above on inputs of this loop {SMPS2}.

> increased storage on output Cap. is likely as response time on the order of one cycle ~ of 50KHz which is faster than loop response time. rough estimate Cmin=dI *dt/dv

I agree to the conclusions as contained in post#2 and post #3.
The closed loop will be stable - in detail: It is "conditionally stable", which means that it will become unstable for lowering the gain.
As mentioned before: If the phase crosses the 0-deg line three times (as in your case), the BODE plot cannot be used for phase margin determination. Instead, the complete NYQUIST plot must be used to judge about stability.

"The problem with a conditionally stable system is that something may cause a gain decrease, for example increased load or decreased line voltage, and this could cause the system to go unstable. This is why conditionally stable systems are testing Power Sources For Stability generally to be avoided, although there are advantages to conditionally stable systems, and their use may be advantageous in some circumstances if analysis shows that they can never become unstable." ©Venable Industries

"As Nyquist proved, if the track of the head of vector goes around the magic point (Av=1) in the counterclockwise direction, even if it exceeded 360° of total phase shift at some point, the system is stable. " ©Venable Industries



I think overshoot to load step response is the key indicator, with worst case tolerances and environmental variances. Unless I knew the load profiles passed all other pertinent specs. I would not accept conditional stable designs.

FYI only

It looks like post #1 shows simulation results. If so, I wonder if the bode diagram and load step response are actually considering the full control system, including effective modulator deadtime? It would be a system with > MHz switching frequency. Otherwise, the results are meaningless and we don't need to discuss about conditional stability.

This reminds me of a problem I tried to solve on a PSU powering the low level stages of 46 TV transmitters of over 10KW output power. The PSUs were laboratory standard 24V 10A with very low noise and ripple (< 1mV). A few times a year one of these would crowbar, the maintenance team would reset the crowbar and they then sprang to life, so would the transmitter!. After a lot of fiddling about, I came to the conclusion that with a certain very short break in the mains feed the output voltage would give an almighty 1/2 cycle of peak transformer voltage (38V?) before settling down to 24V. I spent hours trying to adjust the time constants round the loop to stop this but without building a very high power (40V @10A) pulse generator, there was nothing to be gained. In the end I "adjusted" the crowbar time constant so it would ignore this pulse. Never did see any damage that it might have caused, but it is a bit rough and ready. The other problem that I could not simulate at all was when the transmitter mains had a glitch on it there would have been 100s of amps of current being interrupted so the local ether would have been thick with all sorts of unexpected RF radiation.
Too often I have worked on designs that work when they are on the bench but do not survive mains problems (like this PC ! ).

Frank

Hello all,
I think I can explain this issue now!
the stability of loop should be judged by Nyquist theory! From the picture, it is strange to see that the phase margin<0 when DB>0, while from Nyquist theory, it is totally OK; it allows phase line to down cross and up cross 0 before cut frequence(DB=0)