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Synthesize sram using Synopsys Design Compiler

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Hello.

I'm implementing on-chip memory which is going to be part of micro-architecture.

In this module, I want to use SRAM to implement memory rather than ordinary registers.

But, whenever I synthesize my vhdl code, DC uses flip-flop.

Is there any way to use SRAM in DC? Any comments or links are very helpful.

Thank you.

P.S. For now, I'm using TSMC 45nm library.
 

If you create a memory using VHDL or verilog, DC will synthesize it to flip-flops. Because DC dont have SRAM block to map with the memory structure in the VHDL code you designed. Normally, in order to use SRAM or any other memory such as ROM, you need a memory compiler (from a foundary) which will generate a memory block and then you will set the DC setup file (set link_library) to point out to the memory block such that it can mapped the memory structure in VHDL code to the memory block from the memory compiler.

Thanks.
 
Thanks for pointed out. I didnt know that. Can we mix the 45 nm technology for logic with 40 nm memory block in a die?

Thanks
 

I think tsmc 40nm is a shrink of 45nm. Based on that you can mix it.
 

I have FE Files generated from ARM Memory Compiler. These are couple of files with .dat extention. Now I am confused about how to use them in Synopsys Design Compiler for synthesis. I have top level verilog RTL in which I have instantiated 8kx4 RAM. For this 8Kx4 RAM, I want to use the memory generated by ARM Memory Compiler. Any one know how to use it?. Below is the top few lines of the files generated by ARM Memory Compiler.

# FE Release Version: 3.4.15
# lang compiler Version: 3.0.4
# High Density Single Port SRAM RVT-HVT-RVT Compiler
# CLN40G 40nm Process, RAM-SP Datatable, Version r11p2
# 256 Rows Per Bank, 0.299um^2 Bit Cell
# Copyright 1993-2012 ARM Limited. All Rights Reserved
# Instance Name=
 

In the RTL code, use the memory name you use when generating it in the ARM memory compiler. Eg. in memory compiler, the memory name is 8Kx4, then in the RTL code, you just use the same name to instantiate it, eg. 8Kx4 ram_instan (port_list). Then set the correct path pointed to the 8Kx4.db library (from the memory compiler from the memory) in the set link_library setting in .synopsys_dc_setup. That's all.
 

Thanks a lot Hairo,

However, I don't have any .db file for memory. Memory-Compiler generated .dat files (FE views). Do I just change the extension or use the dat file as it is?
 

If you have ARM memory compiler, you should be able to generate several files for the memory: LEF file, LIB file, Verilog file. Using the LIB file, you can convert the DB format using DC command, read_lib and then write_lib memory_lib_name -format db.

I dont know how the memory compiler generated .dat files. I dont know what is FE?
 

Thnks Hairo,

I now have Synopsys compatible .lib files generated by ARM Memory compiler. However, to instantiate the design in my RTL, do I also have to generate verilog file?. Is there any info in .lib files that tell me the exact port list and dimensions?. At the moment, I only know the instance name of my RAM.


Regards
 

You should generate the verilog file of the memory in order to do simulation. You can get the port list from the generated verilog file as well as the module name which you will use it for memory instantiation in your rtl code.
 

You should generate verilog files of memory if you are going to simulate your RTL.

For synthesis, the verilog file is not needed, the .lib/.db is enough. The .lib file contains the port list and their dimension, and their direction.
 

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