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How to increase the dc gain of folded cascode ota in 90nm Cmos process??

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HI i am new to the analog based circuit design.. I have been designing folded cascode OTA for 9-bit 200MSPS pipeline ADC in 90nm CMOS technology with the following specifications
power supply =1v
dc gain= 62db
unity gain b/w =1.162Ghz
phase margin =68.38deg

But when i simulate the following ota for dc gain using cadence tool, im nt able to get dc gain above 30db.. Whats wrong with my input specifications..??

Vin+ =800mv ; Vin- = -800mv ; Cl= 500fF
 

The most probably your simulation setup is causing your gain to drop. First check input biasing, DC operating point. Also regulated cascode you have shown may really decrease your output range and as you are working with a 1 V supply it might be problematic.

If you are sure about your simulation setup, the first thing I would look for is the Common Mode Feedback. It might cause your output stage to saturate.
 
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