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SAR ADC Parasitic capacitance of S/H

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Enialis88

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Hello, I design a differential 10 bit SAR ADC and I have a problem with switches. I used a bootstrapped switch for the sampling optimizing it for charge injection. The problem arises when this switch is OFF: its parasitic capacitance creates offset during the switching of the SAR conversion algorithm (capacitors are still ideal for the moment). How can I remove this offset? Thank you. (I am using the Liu Switching Scheme)
 

e switch conductance versus input signal Vin. ?
crosstalk pn Vref. from digital noise of SAR?
Where does it come from?

I think you need a design that has ON-resistance that is nearly constant. How I dont know.
 
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The ON-resistance is nearly constant with the bootstrapped circuit. The problem is in the OFF-state not in the ON-state.
Since the sampling switch is big, it has parasitic capacitance to ground that adds to the capacitor array. This parasitic capacitance creates an offset during the charge redistribution process...now I think at the end it will be only a gain-offset for the ADC but if it is possible to remove it, it will be better.
 

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