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different input logic to FPGA

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Hi

I have to configure the same FPGA spartan III for different logics that is LVDS ,PECL and TTL

Is it possible that few pins of my FPGA are driven on TTL few on PECL and few on LVDS at the same time

regards
uzmeed
 

yes, see the user manual on select io. Some of the older fpga's only have dedicated pins for differential in, differential in clock, and differential out. newer device tend to allow differential IO, but input clocks are still a special case.
 

You can do this in pin package. Goto assign pin package or IO plan ahead....
Each pins can be directed to the required IO standard, but not sure about clock standards....
 

hi

thank u all

now can u please guide me how to configure the pin for the PECL

i m having voltage swing from 1.16 (lo) and 2.068 (hi) in the signal ( with reference to ground) is it right for PECL interfacing to FPGA

regards
uzmeed
 

Hi Buddy, I am not sure about values. An easiest way is to download Xilinx Spartan 3 datasheet and check the electrical characteristics. Maybe you should get the answer in minutes....
 

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