3 Bit Gray Code Counter VHDL Issue

Code VHDL - [expand]
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library IEEE;                    
use IEEE.STD_LOGIC_1164.ALL;     
use IEEE.STD_LOGIC_ARITH.ALL;    
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity counter_3bit_gray is 
    port   (Clock         : in   BIT;
            Reset         : in   BIT;
            Count_Out     : out  BIT_VECTOR(2 downto 0));
  end entity;
 
architecture counter_3bit_gray_arch of counter_3bit_gray is
 
component DFF
    port   (Clock           : in   BIT;
            Reset           : in   BIT;
            D               : in   BIT;
            Q, Qn           : out  BIT);
end component;
 
signal Q2_cur, Q1_cur, Q0_cur      : BIT;
signal Q2n_cur, Q1n_cur, Q0n_cur   : BIT;
signal Q2_nxt, Q1_nxt, Q0_nxt      : BIT;
            
 
  begin
 
     Q2 : DFF port map (Clock => Clock, Reset => Reset, D => Q2_nxt, Q => Q2_cur, Qn => Q2n_cur);
     Q1 : DFF port map (Clock => Clock, Reset => Reset, D => Q1_nxt, Q => Q1_cur, Qn => Q1n_cur);
     Q0 : DFF port map (Clock => Clock, Reset => Reset, D => Q0_nxt, Q => Q0_cur, Qn => Q0n_cur); 
     
     Q2_nxt <= (Q2_cur and Q0n_cur) or (Q2_cur and Q1n_cur) or (Q2n_cur and Q1_cur and Q0_cur);  
     Q1_nxt <= (Q2n_cur and Q1n_cur and Q0_cur) or (Q2n_cur and Q1_cur and Q0n_cur) or (Q2_cur and Q1_cur and Q0_cur) or (Q2_cur and Q1n_cur and Q0n_cur);
     Q0_nxt <= Q0n_cur;
 
     Count_Out(2) <= Q2_cur;
     Count_Out(1) <= (Q2n_cur and Q1_cur) or (Q2_cur and Q1n_cur);
     Count_Out(0) <= (Q1_cur and Q0n_cur) or (Q1n_cur and Q0_cur);
 
end architecture;