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How to do 8B/10B enco/deco for clock signals in Verilog/VHDL

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jay_ec_engg

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8b 10b verilog

Hi friends...
I have 3 clocks I want encode them... How can I encode them...
8B/10B , Manchester or Pulse width ? How to do it in Verilog/vHDL??

Jay
 

8b/10b vhdl

jay_ec_engg said:
Hi friends...
I have 3 clocks I want encode them... How can I encode them...
8B/10B , Manchester or Pulse width ? How to do it in Verilog/vHDL??

Jay
Click to expand...

I think it is not difficult for using VHDL/Verilog

--------Code by verilog----------------
module man_code(clk,in,out);

input in,clk;
output out;
reg out;

always @(posedge clk)
begin
if (in)
out = clk ;
else
out = !clk;
end

endmodule

----------Simulation wave form--------------
 

8b10b verilog

Thanks...!!

What if I have 3 clocks and I want to encode them into single optut???

Please do reply

jay
 

encoder 8b/10b vhd

You can have a reference to some sample code about 8b/10b and manchester endec from xilinx.com. you can also try some ampp core from altera.com if you are altera user.
 

8b/10b verilog

Ya I used altera also.. But I have to use xilinx this time.... and I cant buy core also as per project cost... I have to write code myself... Can u help me for the same...
 

8b 10b encoding verilog

one paper from IBM lab can tell you how to write 8B/10B encoder/decoder. you can search it.
i remember one master's paper is about how to write it.
but it is chinese.
 

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