anishsingh
Junior Member level 2
Hi I am trying to do a synthesis of verilog code by using RTL compiler .. The code got correctly compiled in modelsim but is giving errors while rtl compilation .. I am using ..
parameter signed b0 = 8'b00000011 ;
.. lines in codes to supply constants.. The rtl synthesis is giving the error of b0 being an undeclared variable ! I tried to make ..
reg [7:0] b0;
assign b0 = 8'b00000011 ;
..but again it gives an error that register declaration is not allowed !!
please help !!
parameter signed b0 = 8'b00000011 ;
.. lines in codes to supply constants.. The rtl synthesis is giving the error of b0 being an undeclared variable ! I tried to make ..
reg [7:0] b0;
assign b0 = 8'b00000011 ;
..but again it gives an error that register declaration is not allowed !!
please help !!