ladyfox
Newbie level 3
Hello~
I'm doing sth on pcie with the chip of altera cyclone IV (EP4CGX22F14C7 actually).
The pcie core uses transceivers for the RX and the TX differential signals,
and the 3rd couple of differential signal ,refclk, is used to clock the transceiver partially.
Inside the FPGA, the refclk should be routed to a Multipurpose PLL that adjacent to the CDR in the transceiver.
My problem is that
Are the inputs of the Multipurpose PLL several fixed pins on the chip, or they can just be the normal dedicated clock pins?
i can't find the more detailed info in the datasheet.
could someone help me or tell me where i should go for the information?
regards
I'm doing sth on pcie with the chip of altera cyclone IV (EP4CGX22F14C7 actually).
The pcie core uses transceivers for the RX and the TX differential signals,
and the 3rd couple of differential signal ,refclk, is used to clock the transceiver partially.
Inside the FPGA, the refclk should be routed to a Multipurpose PLL that adjacent to the CDR in the transceiver.
My problem is that
Are the inputs of the Multipurpose PLL several fixed pins on the chip, or they can just be the normal dedicated clock pins?
i can't find the more detailed info in the datasheet.
could someone help me or tell me where i should go for the information?
regards