gundaljk
Newbie level 3
We are designing a two stage Cmos opamp using cadence 180 nm technology.We tried P E Allen Text book procedure but the output is getting saturated.We are not even getting the high gain.Can anybody suggest us the design which will give us around 80db gain.We need it for a comparator in SAR ADC.Please try to give the hand written calculations ASAP.
