Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to load the image into Quartus 2 verilog code??

Status
Not open for further replies.

syuen

Newbie level 1
Joined
Apr 14, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
(urgent) How to load the image into Quartus 2 verilog code??

I am currently doing my final year porject for my study and i am first time using the Quartus II software to write the verilog code for image processing.This is very urgent because my project deadline is end of april 2012.So ,i wish anyone can help me solve the problem.

My project is need to encrypt the image in the verilog code and then display the output at the FPGA board.Now i have face the problem as below:

1. how to load/read the image in the verilog code?what is the command can be use if i save the image pixel in the text file that generate in MATLAB?
2. how i can know that the image that i read are correct or not??

hope anyone that expert in the verilog code can help me solve this problem. Thank!!
 
Last edited:

1) There are several functions in Verilog that allow you to open and read external files ($fopen and $fread) icluding image files. You can use these to open the image file and store the image into internal registers or memory. This only works for simulation though. Does your project require you to implement your design on a real FPGA or is for simulation only?

2) To know if your image file is correct, try to convert a simple image which can be analysed easily by looking at the file, for example an image consisting of only black and white lines. When looking at the file you should see something like "...FFFFFFFFFFFFFF..." in some lines and "...00000000000000..." on others. Then do the same for black and white vertical columns and you should see something like "...FFFF0000FFFFF0000..."
 

A flexible method, that's also used by Altera IP is to write the data in hex format and specify it as init file for an altsyncram block. Alternatively, $readmemb and $readmemh is supported for synthesis of Verilog code with inferred RAM/ROM blocks.
 

Re: (urgent) How to load the image into Quartus 2 verilog code??

hello syuen,

I am also doing my final project on Image processing, BUt i have no idea how i can input an image in verilog?

I want use a JPG file saved on my computer.
 

You didn't clearly tell what you want to achieve:
- read a jpg image in simulation
- include a fixed jpg image to the synthesized FPGA at compile time
- read different jpg images at run time
The two first variants can use $readmemb, the third needs a data interface.
 

Hello,

my professor told me to do project on Image processing in verilog but I dont know anything about FPGA and verilog. I have only 10 days..Please help me.


You didn't clearly tell what you want to achieve:
- read a jpg image in simulation
- include a fixed jpg image to the synthesized FPGA at compile time
- read different jpg images at run time
The two first variants can use $readmemb, the third needs a data interface.[/QUOTE]
 

First of all, tell us if your project is for simulation only or if it will be implemented on a real FPGA.

Second, tell us exactly what your project requires.

10 days to learn Verilog and do an image processing project is tough.

I think that using a JPEG file is too difficult since it needs to be decoded. It is usually much simpler to use BMP files.
 
  • Like
Reactions: sntsh

    sntsh

    Points: 2
    Helpful Answer Positive Rating
You previouly talked about a final year's project. As we all know, it's scheduled for more than 10 days.

If you're starting now to work with FPGA hardware as part of the project, you should be able to get some insights within 10 days. If you say you have 10 days left to start and finish the actual FPGA coding for your project, it's just helpless.,
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top