Alka Arora
Newbie level 6
Hi ,
In VHDL we have a function to convert std_logic_vector to signed data type.Do we have anything like that in verilog to convert in to signed type in verilog.
for example i have wire [8:0] diff;
I want to convert it into absolute value.
Thanks
Alka
In VHDL we have a function to convert std_logic_vector to signed data type.Do we have anything like that in verilog to convert in to signed type in verilog.
for example i have wire [8:0] diff;
I want to convert it into absolute value.
Thanks
Alka