How to do LVDs <-> LVTTL signal conv with FPGA???

lvds to lvttl

Hi friends...
How can I do single endded to differential and differential to signale ended conversion with FPGAs ??
i.e. Can I do LVDS to LVTTL conversion and LVTTL to LVDS conversion with FPGAs??? any xlinx FPGA has this inbuil support ???

ibufds_lvds_25

ALL xilinx vertex types and I beleive spartan 2 and 3.

I know that on the vertex, there are "sectioned" IO reference pins that allow a group of IO pins to be set to a specific voltage. you can change some or all Pins to several different voltage protocols.

I personally have not used it but it is there.

lvttl lvds

So you mean to say that its inbuilt macro kind of thing...??

What my question is I am giving LVDS signals to say Spartan-2 or 3.... and I want LVTTL output... for that I need to write program or there are some macros itself will do the conversion...??? Or it is hardware setting ??

lvds lvttl

You'll need to create, synthesize and route a design, but yes, you can. There are some defines you need to pass to the synthesizer (writing them in your code, or defining constraint file), that tell the IO standard of each pins. Also, note that FPGA work in IO banks. An IO bank can only have one voltage level. So, you put LVDS in one bank, LVTTL in another IO bank.

However, LVDS can have hich signal rate (like 622.08Mbps). If you wish to convert to LVTTL, you better parallelize the signal (ex: 8-bit wide LVTTL, at 77.76MHz, to LVDS at 622.08Mbps).

what is lvttl

Hi guys,

If your input signal is LVTTL for example:

- connected to pin A1 in Bank 1 (for example)

you have to write some HDL to route it to another bank, simple instantiation of your LVDS standard output (search in the library)

for example (X!linx)

OBUF_LVDS
OBUFT_LVDS
...

the input to this module will be your LVTTL input and the outputs your LVDS. Bear in mind that your LVDS output must go to a "differential pair" in the IOs of the chip.

To convert from LVDS to LVTTL is just the same. Now look for

IBUF_LVDS
...

I hope it helps,

-maestor

ibufds lvds_25 xilinx

Ya i got the document from application note.... but what is the difference between obuf and obuft ??? and in case we have DCI option... how reliable it is...??

lvds signal

The difference between OBUF and OBUFT is that OBUFT has got a tri-state input to it.

About DCI, I've had bad and good experiences with it. I am using it now to terminate HSTL in a DDR interface and no problem (2vPro).

If you want to use DCI you need to connect VRN and VRP (X!linx chips) via 50Ohm or 100 Ohm, see App for that.

-maestor

lvttl to lvds

can u give me the application note no...

jay

lvds ibuf

this app could help...

hxxp://www.xilinx.com/bvdocs/appnotes/xapp659.pdf

although more useful is

hxxp://www.xilinx.com/bvdocs/userguides/ug012.pdf

it depends on your device...

regards
-maestor

lvttl lvds

Hi all

who can explain them more clearer ! how to use them if A_p and A _n are couple of LVDS as control signal , In FPGA ,how to identify their's rising edge ,maybe need to convert into LVTTL ??

OBUF_LVDS
OBUFT_LVDS IBUF_LVDS
...

Click to expand...

thank you !

lvttl signals

You can do something like this:
When A_p > A_n, then your Aout signal is high.
When A_p rises (and A_n falls), then Aout will rise.

xilinx ibuf lvds

Thank you echo47

IBUFDS_LVDS_25 ibuf1 (.I(A_p), .IB(A_n), .O(Aout));


May I do just do this!

always @(posedge Aout ) // identify Aout 's rising edge
begin // regard Aout as conversion of A_p and A_n


DATA_OUT <=DATA_IN ;
................................
end

Click to expand...

lvds ibufds

Before using Aout as a synchronous clock, you should pass it through a clock buffer, so all the flip-flops will receive a nice low-skew clock. Your software will probably do that for you automatically, but if not ...

wire Aclk;
IBUFDS_LVDS_25 ibuf1 (.I(A_p), .IB(A_n), .O(Aout));
BUFG buf1 (.I(Aout), .O(Aclk));
always @(posedge Aclk)
...

bidirectional lvds xilinx application note

Thank you echo47

I found this in **broken link removed**

Verilog example
This example contains LVDS input, output, and bidirectional I/O.

module LVDSIOinst (CLK, DATA, Tin, IODATA_p, IODATA_n, Q_p, Q_n) ;
input CLK, DATA, Tin;
inout IODATA_p, IODATA_n;
output Q_p, Q_n;

wire iodata_in;
wire iodata_n_out;
wire iodata_out;
wire DATA_int;
reg Q_p_int;
wire Q_n_int;
wire CLK_int;
wire CLK_ibufgout;
wire Tin_int;


IBUF_LVDS UI1 ( .I(DATA), .O( DATA_int));
IOBUF_LVDS UIO_p ( .I(iodata_out), .T(Tin_int), .IO(IODATA_p),
IBUF_LVDS UI2 (.I(Tin), .O (Tin_int));
OBUF_LVDS UO_p ( .I(Q_p_int), .O(Q_p));
OBUF_LVDS UO_n ( .I(Q_n_int), .O(Q_n));
.O (iodata_in));
IOBUF_LVDS UIO_n ( .I (iodata_n_out), .T(Tin_int), .IO(IODATA_n),
.O ());

INV UINV ( .I(iodata_out), .O(iodata_n_out));
IBUFG_LVDS UIBUFG ( .I(CLK), .O(CLK_ibufgout));
BUFG UBUFG (.I(CLK_ibufgout), .O(CLK_int));

always @ (posedge CLK_int)
begin
Q_p_int <= DATA_int;
end

assign iodata_out = DATA_int && iodata_in;

assign Q_n_int = ~Q_p_int;

endmodule

Click to expand...

Can you help me to explain this , they are LVDS why it just have one Input or Output !can you give some material for study ! whether (OBUF_LVDS OBUFT_LVDS IBUF_LVDS) and (IBUFDS_LVDS_25 OBUFDS_LVDS_25) have some differences ? I just see IBUFDS_LVDS_25 in VirtexII pro user manual but my device is spartan2e so two types primitive confuse me !

lvds input interface verilog

Ah yes, Xilinx makes it confusing! This may help a bit:
**broken link removed**

You can instantiate an LVDS input using several variations of IBUF and IBUFDS, depending on which FPGA type you are using. Read the Libraries Guide section carefully. If it's still confusing, try searching the Xilinx Answer Database for more help like the above link. Beware of old answers, and answers for the wrong FPGA type.

Here are some of the methods that I recall using over the years:

IBUFDS_LVDS_25 ibuf1 (.I(A_p), .IB(A_n), .O(Aout));

IBUFDS ibuf1 (.I(A_p), .IB(A_n), .O(Aout));
and then attach an IOSTANDARD LVDS_25 attribute to it.

IBUF_LVDS_25 ibuf1 (.I(A_p), .O(Aout));
Since the IBUF module has only one input, XST automatically assigns the negative differential input to the correct FPGA pin.

IBUF ibuf1 (.I(A_p), .O(Aout));
and then attach an IOSTANDARD LVDS_25 attribute to it.
Since the IBUF module has only one input, XST automatically assigns the negative differential input to the correct FPGA pin.

Another hint: Use FPGA Editor to view your routed chip. Zoom into the I/O pads and examine the LVDS connections to be sure both wires are connected properly. If you've never used FPGA Editor, this is a great time to try it.

conversion signal lvds

jay_ec_engg said:

Hi friends...
How can I do single endded to differential and differential to signale ended conversion with FPGAs ??
i.e. Can I do LVDS to LVTTL conversion and LVTTL to LVDS conversion with FPGAs??? any xlinx FPGA has this inbuil support ???

Click to expand...

If you don't have any superstitions to Altera , I would like to advice you the Cyclone family. You can put there serialization/deserialization circuits with almost any serialization factor. Appropriate megafunction is provided in the Quartus library.

Regards, YUV.

lvds vs lvttl

jay_ec_engg said:

Hi friends...
How can I do single endded to differential and differential to signale ended conversion with FPGAs ??
i.e. Can I do LVDS to LVTTL conversion and LVTTL to LVDS conversion with FPGAs??? any xlinx FPGA has this inbuil support ???

Click to expand...

i don't know u