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Low power design using SoC encounter

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pavi622

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Hi ,
I am doing Flat implementation of IPs using SoC encounter. If i want to integrate low power design along with the flat implementation how to go about it?

What does CPF mean? What does it contain? How to crate power domains & on wat basis we create power domains?
 

Hi.
CPF is Common Power Format.
It contains power domain , power logic ( Level Shifter , Isolation Cell, State retention Cell, Switch Cell and Control Signals ) , Power Mode and Technology information about Power logic.
We can create power domain by using this command " create_power_domain -name XXX "
power domain is design dependent.

Thanks.
 

Hi evesjh77,

i want to functionally verify the low power design using cpf files

i have a lot of questions regarding cpf

can u please share your information about cpf elobarately.
like what tool is used to compile it.
what is the output file format it comes out after compiling

can we verify this cpf files using specman or only with system verilog (assertions) to verify the functionality of RTL.

if u have any respective information(docs,examples,sites) kindly please send them
 

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