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Difference between n-well and high voltage n-well

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lin134340

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Hello,

In layout design, high voltage device must be generated in high voltage well.
I want to know what's the difference between high voltage n-well and an normal n-well.

The reason why I want to know that is..... In a project, we use SMIC 0.18um technology. In it's DRC rule, it shows that layer NW is n-well for 3.3V/1.8V device while layer NWH is HV n-well.
When generate a 5V device, we should use NWH for it. But the mistake is we draw both NWH and NW for it.(the 5V device are surrounded by both NW and NWH) There is no DRC error for it, so we don't check out the mistake.

What's the difference between high voltage n-well and an normal n-well?Does this error matters? Is it a critical error?
 

High Voltage Nwell are usually more deeper n wider then NormAL nWELL , so their extensions are much wider.
 

thanks, but i am still confused about an overlapping NW and NWH means what?

In another way to ask, does it matters or is it allowed if NW and NWH are overlapping?
 

lin134340 said:
... does it matter or is it allowed if NW and NWH are overlapping?
Click to expand...

Surface doping concentration of an NW is considerably higher than that of an NWH, hence the breakdown voltage of an NW to substrate is much lower than for an NWH, possibly lower than 5V. Additionally the doping concentrations of overlapping nwells add and so create an even lower breakdown voltage.

--> For 5V transistors, only use the NWH !
 
Actually, the result of test is more complex.

Anyway, this helps a lot.
 

HV n-well is use for High voltage, normal n-well is using for low voltage.

Why?

Because of the LATCH UP~ it will cause your device burned. In short word, high reverse bias voltage in normal well will cause LATCH UP"something like short circuit" and burn your IC.

You can find out more about Latch Up, then you know why they differentiate the HV well and normal well.

Hopes help~ :)
 
TuAtAu said:
high reverse bias voltage in normal well will cause LATCH UP
Click to expand...
Why?A high reverse bias voltage is more possible to cause a latch up?

OK, suppose it does. Than, hv n-well is few possible to cause latch up than normal n-well.
BUT.....If the doping concentration of hv n-well is smaller than normal n-well, than the parasitic resistor of hv n-well is larger than that of normal n-well. So, hv n-well is more possible to cause latch up.
what's wrong with me?
 

basically 12V/breakdown in normal n well CMOS is good enough to burned. Typically only support TTL 5V or other lower voltage.

For HV well, it is deeper the well i think, so I give deeper space for diffusion. Thus is should be able to handle around 12V / breakdown

"doping concentration of hv n-well is smaller than normal n-well" this 1 I am not sure.

But since the well is deeper, I guess the channel (when 'on') can go even deeper, Thus larger channel is lower resistance and less heat dissipated.. Something like that.

Hopes help~ :)
 

Hi Erik,

Can you please help with understanding why WHN is low doped with respect to NW ? Any supporting document will be more than help .
THanks
Deepak.
 

Which is heavily doped!! NW o NWH.. I think NWH.

- - - Updated - - -

TuAtAu said:
Thus larger channel is lower resistance and less heat dissipated.. ~ :)
Click to expand...

Larger channel in terms of area or length??
 

deepak242003 said:
... why WHN is low doped with respect to NW ? Any supporting document will be more than help .
Click to expand...

Actually the doping concentration isn't decisive for the breakdown voltage: the junction depth is.

The lightly doped side of a pn-junction defines its max. breakdown voltage (BV). The substrate is always the lightly doped side. The actual BV of diffused or implanted (erfc, linearly, or retrograded) pn-junctions depends on the concentration gradient at the junction, which - rather independent of the maximum concentration - is as smaller as deeper the junction is, i.e. as deeper the junction, as higher is its BV.

You may find these relationships in any book about physics and/or technology of semiconductor devices, e.g. in A.S. Grove: "Physics and Technology of Semiconductor Devices" (Wiley, N.Y., 1967) chap. 6.7 Junction Breakdown.
 

Thanks Erikl for the explanation . It is really interesting for me to understand this in more detail .
I tried searching the mentioned book ,but cant find the free ebook version ..
It will be great help if you have that book handy or similar papers and upload it here ... :)
 

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