clock balancing & dft

Hi,

With scan_mode sdc, how the clock balancing is done in Physical Design?
Because, there might be different functional blocks running with different frequencies in a chip and the at-speed clock will be the highest frequency clock.

My discussion points are,
1. During capture mode, low frequency domains are still trying to meet with at-speed(high frequency clock) clock. Does this over constrain that functional block?
2. Or, there will be different at-speed test clock frequencies for each domains running with different frequencies.
3. If that is the cause, DFT at-speed testing is done independently for each domain? or multiple frequencies are used to take care CDC(clock domain crossing).
4. In a design, a single scan chain can be used to stitch flip-flops running with different frequencies?

Thanks,
Eden

Just answering your point number 4. single scan chain cannot use different frequencies. Usually the methodology is to mux single test clock instead of different frequency clock in a single scan chain. To take care of data path across CDC during scan capture (functional) step, DFT lock up latches are inserted in CDC.

morris_mano said:

Just answering your point number 4. single scan chain cannot use different frequencies. Usually the methodology is to mux single test clock instead of different frequency clock in a single scan chain. To take care of data path across CDC during scan capture (functional) step, DFT lock up latches are inserted in CDC.

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Hi morris_mano,

Thanks for your answer. For more clarity, I would like to elaborate the question 4.
4. In a design, a single scan chain (running with same test clock) can be used to stitch FFs running with different (functional) frequencies?

From your reply I assume the answer is yes. That is why we use DFT lock up latches. It will take care the hold violation at the CDC point in shift mode. If that is the cause, how a functional domain running with a low (functional) frequency can meet the at-speed dft capture (running with an at-speed test clock frequency which is higher than the functional frequency).

Thanks
Eden

Eden,

During synthesis, you need to feed SDC for both functional and test mode. Synthesize the design that converge on timing which meets both functional and test mode. After post layout, again do STA to meet design timing requirements for both mode. This will ensure the datapath is short enough to not violate setup for low(functional) frequency and long enough to not violate hold for at-speed test clock frequency.