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have a doubt in execution of process- VHDL

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revooridinesh

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stmnts inside process will execute when sensitivity list changes r8 ? suppose one of variable in sensitivity list changed so the statements of process will execute sequentially one by one, so when the execution is at some line(suppose 4th line) in the code and if a variable in sensitivity list changes so the execution goes to first line of process code or it executes from 4th line ?

Thank You
 

It is important to understand that what's implemented is digital circuit, which is different from a processor executing sequentially.
For example, if what you implemented is a flipflop with asynchronous reset, even though it is about to latch a data (let's say at 4th line), if the reset is active (2nd variable in the sensitivity list), it will reset the output.
 

firstly, this is why "signals" and non-blocking assignments are used. In this case, each process is evaluated but signals are not changed. only after all processes have been evaluated are the values of the signals changed. "shared variables" are not commonly used, but would be subject to race conditions -- shared variables only have blocking assignes, so it isn't clear if a process assigning a shared variable will be evaluated before one that reads it. This isn't normally an issue, as shared variables are not typically used in synthesizable code.
 

In addition, you have been asking for "execution" order (the usual HDL term is evaluation) of statements in a sequential block. The statements are evaluated in a fixed linear order. If the sensitivity list condition is true, the process is scheduled. Please notice also, that sensitivity lists are ignored in hardware synthesis.
 

thank you all for the reply
@FvM If the sensitivity list condition is true, the process is scheduled-- so it is scheduled to what instant ? after completing all stmnts in process ?
 

stmnts inside process will execute when sensitivity list changes r8 ? suppose one of variable in sensitivity list changed so the statements of process will execute sequentially one by one, so when the execution is at some line(suppose 4th line) in the code and if a variable in sensitivity list changes so the execution goes to first line of process code or it executes from 4th line ?

Just to be clear, your use of 'variables' in all of the above is not correct, it should be signals. Now on to your questions regarding if a signal is changed while a process is executing: Example 1, signal xyz is listed in the sensitivity list and it gets assigned to somewhere in the middle of the procees

Code VHDL - [expand]
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Example_1 : process(xyz)
begin
   ...
   xyz <= ...
   ... Some other statements, but not any form of 'wait'
end process Example_1;



What happens: Signal xyz does not change at the point in the process where you see the assignment. All that happens on that statement is the simulator will schedule that signal to change. As shown, the process can have other statements (but in this example, not a 'wait' statement). The code in the process continues until it hits the end of the process. The simulator evaluates all other processes that might also have been triggered at the time of the first change on xyz (i.e. the one that caused the Example 1 process to 'wake up'). At this time, xyz still has not been changed to the new value mentioned in the Example 1 process. Eventually though the simulator evalutates all other processes and is ready to advance. At this point, signal xyz is updated to the new value assigned by Example 1 process and since xyz is in the sensitivity list it will cause the process to trigger again. Note though that the process completed, it did not get interrupted in the middle or anything as you were supposing.

Now you might ask what happens if you do include some form of wait statement


Code VHDL - [expand]
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process(xyz)
begin
   ...
   xyz <= ...
   wait for 1 us;
   ... Some other statements, but not any form of 'wait'
end process;



Actually, this is not legal and the compiler will complain, you can't have both a sensitivity list and a wait statement. So the actual form would have to be the following for Example 2:

Code VHDL - [expand]
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Example_2 : process
begin
   ...
   xyz <= ...
   wait for 1 us;
   ... Some other statements
end process Example_2;



Now your question is moot since there is no sensitivity list, but just to finish it off: Example 2 embeds an assignment to xyz with a following wait statement which is then followed by other statements. The simulator when it hits the assignment will do the same as it did in Example 1 (i.e. schedule an event to occur), but now once the wait statement is hit, the process will suspend. The simulator will then move on to evaluating other processes (just like Example 1 when that process completed), signals will then get updated and the simulator will continue on. Example 2 process will wait for the prescribed period (1 us in this case). Once that time has expired, the simulator will start executing the Example 2 process where it left off (i.e. the statement following the 'wait' statement). Note though that since there is no sensitivity list in this case (there can't be because of the 'wait') it is not the situation you were describing.

Kevin Jennings
 

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