design pll and filter

Hi
I want to design a PLL,and i dont know how can i design a first order low pas filter,i cant use matlab functions,and i want to write a filter my self,below i have a matlab code. i want use it as part of a squaring loop block for carrier recovery in ssb modulation,in this structure fc goes to 2fc and a pll use to phase recovery , how can i design filter same following code? what is kp and ki?indexes of filter? i would appreciate if anybody can help me.


f=1000;%Carrier frequency
fs=100000;%Sample frequency
N=5000;%Number of samples
Ts=1/fs;
t=(0:TsN*Ts)- Ts);
%Create the message signal
f1=100;%Modulating frequency
msg=sin(2*pi*f1*t);
kf=.0628;%Modulation index
%Create the real and imaginary parts of a CW modulated carrier to be tracked.
Signal=exp(j*(2*pi*f*t+2*pi*kf*cumsum(msg)));%Modulated carrier
Signal1=exp(j*(2*pi*f*t));%Unmodulated carrier
%Initilize PLL Loop
phi_hat(1)=30;
e(1)=0;
phd_output(1)=0;
vco(1)=0;
%Define Loop Filter parameters(Sets damping)
kp=0.15; %Proportional constant
ki=0.1; %Integrator constant
%PLL implementation
for n=2:length(Signal)
vco=conj(exp(j*(2*pi*n*f/fs+phi_hat(n-1))));%Compute VCO
phd_output=imag(Signal*vco);%Complex multiply VCO x Signal input
e=e(n-1)+(kp+ki)*phd_output-ki*phd_output(n-1);%Filter integrator
phi_hat=phi_hat(n-1)+e;%Update VCO
end;

formulae as I recall from the late 70's for Loop filter get complicated for capture range , phase noise reduction of clock or stability .
Modelling is required by trial and error as there is a trade-off between desired capture time and jitter reduction as well as capture range and clock error.
You need to define these parameters before you can choose an optimal design.

i really thank you .

if you research web for factors above you may find formulae, graphs to get idea of tradeoffs