Delta modulation integrator frequency range selection

I have designed a delta modulator using a comparator followed by D F/F. The output of the D F/F is given as the input to the integrator and the output of the integrator is given as one of the input to the comparator (that I have stated in the beginning). The other input of the comparator is the sine wave.

The output of the D-F/F is the modulated output, right?

I have one more doubt. I have to select the integrator frequency range from which I will find out the values of the resistances needed.I am a bit confused because the output of the D F/F is periodically done by a clock given to the D F/F. But at the same time the wave from the D F/F need not have the same frequency as that of the clock. I think it's somewhat related to the signal frequency. At the same time the output is a square wave. How to find out this frequency range? or What is the exact frequency range of the integrator?

Thanks in advance.

The output of the D-F/F is the modulated output, right?

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Yes. The output of a (1-bit) sigma delta modulator is a binary sequence representing the input signal. It's usually processed in a multi stage decimation filter to get the final output signal.

The term "frequency range of the integrator" doesn't seem to make sense. You'll notice, that the output sequence shows different patterns changing with the input level, also for static input voltage.

FvM said:

Yes. The output of a (1-bit) sigma delta modulator is a binary sequence representing the input signal. It's usually processed in a multi stage decimation filter to get the final output signal.

The term "frequency range of the integrator" doesn't seem to make sense. You'll notice, that the output sequence shows different patterns changing with the input level, also for static input voltage.

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I was talking about the unity gain frequency which is given by 1/RC. So I have to correctly select R and C. How to do that?

You'll find the answer in basic SD literature, e.g. Schreier et al. The integrator time constant plays the role of a feedback gain for SD modulators. G = 1/(T*f) with integrator time constant T and sampling frequency f. First order modulators run well with a gain around unity.

P.S.: Playing around with a simple SD simulation, either in Matlab, SPICE or a spreadsheet calculators is probably more instructive than lengthy discussions.

FvM said:

You'll find the answer in basic SD literature, e.g. Schreier et al. The integrator time constant plays the role of a feedback gain for SD modulators. G = 1/(T*f) with integrator time constant T and sampling frequency f. First order modulators run well with a gain around unity.

P.S.: Playing around with a simple SD simulation, either in Matlab, SPICE or a spreadsheet calculators is probably more instructive than lengthy discussions.

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So you mean the integrator frequency is dictated by the clock frequency (which is the sampling frequency) and not by the input signal frequency, right?

Thank you.

So you mean the integrator frequency is dictated by the clock frequency (which is the sampling frequency) and not by the input signal frequency, right?

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Yes, absolutely. You'll also notice, that you get sloppy response with G < 0.7, ringing with G > 1.3 and self oscillation for G >= 2.