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Please see the Image , this is a post layout simulation result at 6 GHz for a CMOS Mixer with Calibre, Assura and Schematic(without post layout), as you can see it seems that both Assura and Calibre have the same results. (Technology : 90nm)
Going to higher frequency, I can definite see significant difference in Calibre and Assura extraction.
Calibre extraction has been adding extra gate resistance somehow (for a tsmc kit), I don't quite understand why it does that.
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