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[SOLVED] post-layout sta problems

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soloktanjung

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Hi,

I have timing analysis problems for post-layout sta using primetime. This is the part of the report:

Code: 
  Startpoint: .../ctrl_in_ack_rx_o_reg                                                                                                                              
               (rising edge-triggered flip-flop clocked by clk_i)
  Endpoint: dmem_en_out
               (output port clocked by clk_i)
  Path Group: clk_i
  Path Type: max

  Point                                                   Incr       Path
  ------------------------------------------------------------------------------
  clock clk_i (rise edge)                             0.00       0.00
  clock network delay (propagated)             2.40       2.40
  .../ctrl_in_ack_rx_o_reg/CK (EDFFTRX1TL) 0.05 &     4.07 r
  ...
  ...
  ...
  dmem_en_out (out)                                0.03 &    5.70 r
  data arrival time                                                  5.70

  clock clk_i (rise edge)                             4.00       4.00
  clock network delay (propagated)             0.00       4.00
  clock uncertainty                                   -0.40       3.60
  output external delay                             -0.50       3.10
  data required time                                                3.10
  ------------------------------------------------------------------------------
  data required time                                                3.10
  data arrival time                                                 -5.70
  ------------------------------------------------------------------------------
  slack (VIOLATED)                                                 -2.60

My sdc constraints:
Code: 
create_clock [get_ports clk_i]  -period 4  -waveform {0 2}
#set_clock_latency 2.5  [get_clocks clk_i] -- for place and route stage
#set_clock_latency -source 2.5  [get_clocks clk_i]
set_clock_uncertainty 0.4  [get_clocks clk_i]
#set_clock_transition -rise 0.13 [get_clocks clk_i]
#set_clock_transition -fall 0.13 [get_clocks clk_i]

set_propagated_clock [all_clocks]

Question is: Why is clock network delay (propagated) in the captured path is zero while in the launch path is 2.40 (it has value). Is it any problem with my sdc constraints?

Check_timing only reported issues regarding no_driving_cell.

Thanks in advance.
 

Yes, it is a problem in your SDC. As you can see, the endpoint of your path is output port (not a flip-flop). So, when you type command set_propogated_clock, the tool see the real path (and calculate latency) from input clock port to each flip-flop in your design. But, it does not see the path from input clock port to the output port. Such path does not exist in the block netlist. It only be observable on top level of hierarchy.

So, usually in such case (when you load in the tool only one block of hierarchical design), you may set by command set_clock_latency the clock latency for all output/input ports, the value for this latency you may calculate as average of clock latencies for each flip-flop in your block.

Try to uncomment the commented lines in your SDC code (set_clock_latency and set_clock_transition).
 
Yes that's right. There are problems in the SDC related to the clock for IO constraints. Thanks for your suggestion. I solved it by creating virtual clock for constraining IO ports because it is better to control the IO constraints for post-layout timing analysis. This virtual clock has clock source latency (will be used for IO timing calculations) while the propagated clock has no clock source latency (it uses the propagated network latency from clock tree).

Thank you.
 
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