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That depends on whether you a re talking about combinatorial or sequential logic, and how complete your non-default case branch statements are. For combinatorial logic, you need to make sure that variables you are writing to are assigned at least once given every possible path through your process. If there are unspecified case branches, and the case statement is the only place you write to a variable, you need a default statement to make assignments to all variables to insure they do not turn into a latch.
Search for full case versus parallel case topics in Verilog or VHDL.
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