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[FPGA]Using RAM Block as CACHE (VHDL)

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TuAtAu

TuAtAu

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[SOLVED][FPGA]Using RAM Block as CACHE (VHDL)

Hi, I am facing 2 problems, need some advice.

1. I have 2MB BRAM , can I sperate them 1MB to instructions 1MB to data for my softcore cache?
or it must use it in full 2MB?

2. If it is able to do it, how to do it in VHDL. I dont want to use coregen. I want to learn how to program the BRAM by using VHDL.. any reference or details?

Thanks in advance!


APPENDIX:
Model: Xilinx Spartan-3A DSP, XC3SD3400A-4FGG676C
• DSP Performance: 32 GMACS
• Maximum DSP frequency: 250 MHz
• Block RAM: 2,268 Kb
• Logic cells: 53,712
• Speed: 213 × 622+ Mbps LVDS pairs
 
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BRAMs are not one big solid memory, but lots and lots of small ones (IIRC, they are 9K bits per ram). They can be configered to any combination of data and address, eg. 8k x 1bit up to 256x32 bit. You can infer BRAMs from VHDL, and the synthesisor will place as many ram primitives as are required to make the ram you need (so you could create a massive 2Mb one, or just a tiny one).

For Xilinx, read this document, chapter 3, on how to have elements infered from VHDL (rather than use the core gen). They provide templates to make sure things are done correctly:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf (this is V11, there probably are newer ones out there, but this is what came up on google first)
 

    TuAtAu

    TuAtAu

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