satyakumar
Full Member level 3
system verilog training in hyderabad
Full time course on Verification Using SystemVerilog - Hyderabad
Venue:
When: Batches starts on every Saturday at 11 AM
Where: Hyderabad
Cost: Rs. 10000 /- onwards (See below for details)
Contact: training @ neoschip.in, +91-8886714111, +91-40-66567676
What’s SystemVerilog?
IEEE 1800, SystemVerilog is the language used for Digital system Verification (and Design). With size shrinking of CMOS technology has led to increased complexity of chip design by packing more functionality, And it became too complex to verify the complete functionality of the chip. This requires robust yet powerful verification languages. In today’s semiconductor industry almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.
Who should attend?
Fresh graduates who wish to start their VLSI career as verification engineer.
Practicing Design and Verification engineers, and working people .
How do I register for a class?
To attend this class, confirm your registration by sending an email
to training @neoschip.in +91-8886714111, +91-40-66567676
Please include the following details in your email:
Name:
Company/college Name:
Official/personla Email ID:
Contact Number:
Preferred Date: To join
Trainer Profile
Suresh kumar, Senior Design Verification Consultant
* Has 9+ years of experience in Verification
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on SystemVerilog, OVM, VMM, UVM
and OOP for Verification
* Holds M.Tech from IIT, Bombay.
Full time course on Verification Using SystemVerilog - Hyderabad
Venue:
When: Batches starts on every Saturday at 11 AM
Where: Hyderabad
Cost: Rs. 10000 /- onwards (See below for details)
Contact: training @ neoschip.in, +91-8886714111, +91-40-66567676
What’s SystemVerilog?
IEEE 1800, SystemVerilog is the language used for Digital system Verification (and Design). With size shrinking of CMOS technology has led to increased complexity of chip design by packing more functionality, And it became too complex to verify the complete functionality of the chip. This requires robust yet powerful verification languages. In today’s semiconductor industry almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.
Who should attend?
Fresh graduates who wish to start their VLSI career as verification engineer.
Practicing Design and Verification engineers, and working people .
How do I register for a class?
To attend this class, confirm your registration by sending an email
to training @neoschip.in +91-8886714111, +91-40-66567676
Please include the following details in your email:
Name:
Company/college Name:
Official/personla Email ID:
Contact Number:
Preferred Date: To join
Trainer Profile
Suresh kumar, Senior Design Verification Consultant
* Has 9+ years of experience in Verification
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on SystemVerilog, OVM, VMM, UVM
and OOP for Verification
* Holds M.Tech from IIT, Bombay.
