Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem while locking PLL for 6GHz

Status
Not open for further replies.
A

Ayyanar M

Junior Member level 1
Joined
Aug 2, 2011
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,393
Hi,

I done a PLL for 6GHz and its not get locked. That is control voltage gets down after settling time. Pls see the snap i attached and give me a solution. It is 3rd order Charge pump - pbm.pngPLL
 

Is your control loop stable? Did you take the loading from the VCO side in to account while you designed the loop filter?
 

yes loop is in stable. I got phase margin as 65 deg and Loop bandwidth 600KHz for 20MHz ref frequency. And also i have taken account of VCO load. Whatever the loop parameters,the control voltage gets affected @15us constantly.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top