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LVDS Recevier Circuit Alternatives

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rreddy

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Hi,

I was looking at circuits that receive LVDS signals and convert them to single ended signals on intergrated circuit (CMOS or BiCMOS technology). I have come across the following journal which appears to be popular:

Boni, Pierazzi and Vecchi (2001), "LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35- m CMOS".

It is based on Schmitt trigger. Tuning the hysteresis in the circuit is quite tricky.

Does anyone know an alternate approach?
 

Perhaps building onto the original question. Are LVDS pads often designed from scratch or are LVDS 3rd party pads typically purchased and used?

If you had a ASIC design requiring a LVDS receiver and assume the LVDS transmitter is an FPGA. Also assume the purchasing of 3rd party IP isn’t a feasible option. Would you:

a) Design your own LVDS receiver?
b) Use another differential I/O standard?
c) Use another single ended I/O standard?
or something else?
 

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