aroy
Newbie level 5
I am working with a custom board that will be used for evaluating the performance of two measurement ADCs (AD9649 & ADS6143) at high temp. The output of the ADCs is connected to a Cyclone 3 FPGA. An SPI interface is used to gather data from the FPGA and log it into a computer. What I currently have is the following:
1. A 2^14 length FIFO buffer inside the FPGA that stores 32-bit data (16-bits from each ADC). 16-bits comes from: 14-bit data + 1 overflow bit + 1 parity bit
2. the fpga acts as an SPI slave that responds to data sent from the computer. The bitrate is 1 MHz. I can set this to a maximum of 8 MHz. I have verified that the SPI module is working properly.
3. The FPGA clock is 48 MHz.
4. there is a 9 us setup time between each byte sent to the fpga via the MOSI bus (this cannot be avoided since it is a feature of the Aardvark SPI adapter I have to use).
I store a sample from each ADC into the buffer on every rising edge of the fpga clock. It takes 341us to fill the buffer whereas 59us (32 + 9*3) to read just one memory location in the buffer. once i reach the end of the buffer i go back to the beginning, but this overwrites unread data.
even if i increase the bitrate to 8 MHz, the problem would still remain. is there any way other than slowing down the read speed to prevent data from being overwritten in the buffer. one possibility is to wait until all data is read from the buffer before re-writing, but this means I lose a lot of samples. According to Quartus, my current setup uses 86% of the FPGA memory and I do not have SRAM or DRAM.
Any thoughts on this is greatly appreciated!
1. A 2^14 length FIFO buffer inside the FPGA that stores 32-bit data (16-bits from each ADC). 16-bits comes from: 14-bit data + 1 overflow bit + 1 parity bit
2. the fpga acts as an SPI slave that responds to data sent from the computer. The bitrate is 1 MHz. I can set this to a maximum of 8 MHz. I have verified that the SPI module is working properly.
3. The FPGA clock is 48 MHz.
4. there is a 9 us setup time between each byte sent to the fpga via the MOSI bus (this cannot be avoided since it is a feature of the Aardvark SPI adapter I have to use).
I store a sample from each ADC into the buffer on every rising edge of the fpga clock. It takes 341us to fill the buffer whereas 59us (32 + 9*3) to read just one memory location in the buffer. once i reach the end of the buffer i go back to the beginning, but this overwrites unread data.
even if i increase the bitrate to 8 MHz, the problem would still remain. is there any way other than slowing down the read speed to prevent data from being overwritten in the buffer. one possibility is to wait until all data is read from the buffer before re-writing, but this means I lose a lot of samples. According to Quartus, my current setup uses 86% of the FPGA memory and I do not have SRAM or DRAM.
Any thoughts on this is greatly appreciated!
