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question : settling time for SAR A/D reference buffer

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cmos_ajay

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I need to design a reference buffer for a successive approximation ADC. This ADC uses a capacitive DAC array. What is the procedure to determine the reference buffer specifications such as gain , bandwidth, settling time etc. ??
Is there a document outlining this ??
 

cmos_ajay said:
What is the procedure to determine the reference buffer specifications such as gain , bandwidth, settling time etc. ??
Click to expand...

No special requirements concerning gain & bandwidth. Settling time appropriate for your own requirement (time to stability after enabling).

But: input offset voltage < 1LSB
-- except that you are able to trim each chip individually, or if you use an architecture which is independent of the absolute value of the reference voltage.
 

Hello,
SAR - ADC clock period = 1/20Mhz
LSB size = Vref / 4096 for a 12 bit ADC
So if VREF = 2.5V, then LSB is 600uV
As a general rule the settling must be within (1/2)LSB in (1/2) clock period

Is there any ADC reference buffer architecture that can fulfill such a tight requirement ?? Should I use a voltage regulator which has a fast load regulation response ??
 

Hello, I agree it has to be a unity gain buffer. Based on the ADC specifications like 12 bits, 20Mhz clock, settling time and offset less than 1 LSB, is there a way to determine the required Opamp gain ?? Can someone clarify this ?
 

Is it necessary to use a class AB amplifier for the buffer stage ??
 

cmos_ajay said:
Is it necessary to use a class AB amplifier for the buffer stage ??
Click to expand...
In order to control the cross-current, I'd suggest so. OpAmp gain is no issue, 40..60dB is enough.
 

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