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[Moved] error:this signal is connected to multiple drivers

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vvarlord

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i wrote this code but i'm gettin the error :" this signal is connected to multiple drivers "

here's my code:



Code:
module executer(ins,clk
    );
input [9:0] ins;
input clk;
reg re,we,ie;
reg [2:0] i,ar1,ar2,aw,op;
reg [3:0] w,a,b;
wire [3:0] r1,r2,out;
wire c,v,n,z;
always @(negedge clk)
if(ins[9]==1)
begin
ar1=ins[5:3];ar2=3'b000;aw=3'b000;re=1;we=0;ie=1;i=ins[2:0];w=4'b0;
end
else
begin
ar1=ins[5:3];ar2=ins[2:0];aw=3'b000;re=1;we=0;ie=0;i=3'b000;
end
always @(posedge clk)
begin
ar1=3'b000;ar2=3'b000;aw=ins[5:3];re=0;we=1;ie=0;i=3'b000;w=out;
end
registerfile u1(.ar1(ar1),.ar2(ar2),.re(re),.aw(aw),.w(w),.we(we),.clk(clk),.r1(r1),.r2(r2));
alu u2(.a(r1),.b(r2),.op(ins[8:6]),.out(out),.c(c),.n(n),.z(z),.v(v));
endmodule

.........................
module alu(a,b,op,out,c,n,z,v
    );
input [3:0] a,b;
input [2:0] op;
output reg [3:0] out;
output reg z,n,v,c;
reg [2:0] x;
reg c3;
always @*
if (op[2:1]==2'b00)
	begin
		case (op[0])
		1'b0: {c,out}=a+b;
		1'b1: {c,out}=a-b;
		endcase
	{c3,x}={{a[2:0]}-{b[2:0]}};v=c^c3;z = out?1'b0:1'b1;n = {out[3]}?{1'b1}:{1'b0};
	end
else
	begin
		case(op)
		3'b010: out=a&b;
		3'b011: out=a|b;
		3'b100: out=a^b;
		3'b101: out=~a;
		3'b110: out=~(a&b);
		3'b111: out=~(a|b);
		default: out=4'b000;
		endcase
	z = out?{1'b0}:{1'b1};n = {out[3]}?{1'b1}:{1'b0};c=1'bx;v=1'bx;
	end
endmodule
...................
module registerfile(ar1,ar2,aw,re,w,we,clk,r1,r2,ie,i );
	 input re,we,clk;
	 input [2:0] i,ar1,ar2,aw;
	 input [3:0] w;
	 input ie;
	 output reg [3:0] r1,r2;
	 reg [3:0] rf [0:7];
	 reg [3:0] k;
	 initial
	 begin
	 for (k=0;k<8;k=k+1)
	  	 rf[k]=4'b0;
    end
	 always @(posedge clk)
	 if (we==1)
	 begin
	 rf[aw]=w;
	 end
	 always @(negedge clk)
	 
	 if (re==1)
    begin
    r1=rf[ar1];
	 r2 = ie?i:rf[ar2];
	 end
	 else
	 begin
	 r1=4'bx;r2=4'bx;
	 end
endmodule
 
Last edited by a moderator:

i wrote this code but i'm gettin the error :" this signal is connected to multiple drivers "

here's my code:



Code:
module executer(ins,clk
    );
input [9:0] ins;
input clk;
reg re,we,ie;
reg [2:0] i,ar1,ar2,aw,op;
reg [3:0] w,a,b;
wire [3:0] r1,r2,out;
wire c,v,n,z;
always @(negedge clk)
if(ins[9]==1)
begin
ar1=ins[5:3];ar2=3'b000;aw=3'b000;re=1;we=0;ie=1;i=ins[2:0];w=4'b0;
end
else
begin
ar1=ins[5:3];ar2=ins[2:0];aw=3'b000;re=1;we=0;ie=0;i=3'b000;
end
always @(posedge clk)
begin
ar1=3'b000;ar2=3'b000;aw=ins[5:3];re=0;we=1;ie=0;i=3'b000;w=out;
end
registerfile u1(.ar1(ar1),.ar2(ar2),.re(re),.aw(aw),.w(w),.we(we),.clk(clk),.r1(r1),.r2(r2));
alu u2(.a(r1),.b(r2),.op(ins[8:6]),.out(out),.c(c),.n(n),.z(z),.v(v));
endmodule

.........................
module alu(a,b,op,out,c,n,z,v
    );
input [3:0] a,b;
input [2:0] op;
output reg [3:0] out;
output reg z,n,v,c;
reg [2:0] x;
reg c3;
always @*
if (op[2:1]==2'b00)
	begin
		case (op[0])
		1'b0: {c,out}=a+b;
		1'b1: {c,out}=a-b;
		endcase
	{c3,x}={{a[2:0]}-{b[2:0]}};v=c^c3;z = out?1'b0:1'b1;n = {out[3]}?{1'b1}:{1'b0};
	end
else
	begin
		case(op)
		3'b010: out=a&b;
		3'b011: out=a|b;
		3'b100: out=a^b;
		3'b101: out=~a;
		3'b110: out=~(a&b);
		3'b111: out=~(a|b);
		default: out=4'b000;
		endcase
	z = out?{1'b0}:{1'b1};n = {out[3]}?{1'b1}:{1'b0};c=1'bx;v=1'bx;
	end
endmodule
...................
module registerfile(ar1,ar2,aw,re,w,we,clk,r1,r2,ie,i );
	 input re,we,clk;
	 input [2:0] i,ar1,ar2,aw;
	 input [3:0] w;
	 input ie;
	 output reg [3:0] r1,r2;
	 reg [3:0] rf [0:7];
	 reg [3:0] k;
	 initial
	 begin
	 for (k=0;k<8;k=k+1)
	  	 rf[k]=4'b0;
    end
	 always @(posedge clk)
	 if (we==1)
	 begin
	 rf[aw]=w;
	 end
	 always @(negedge clk)
	 
	 if (re==1)
    begin
    r1=rf[ar1];
	 r2 = ie?i:rf[ar2];
	 end
	 else
	 begin
	 r1=4'bx;r2=4'bx;
	 end
endmodule

What signal is it complaining about? You need to find why it has two drivers... that's not allowed.
 
i wrote this code but i'm gettin the error :" this signal is connected to multiple drivers "

here's my code:



Code:
module executer(ins,clk
    );
input [9:0] ins;
input clk;
reg re,we,ie;
reg [2:0] i,ar1,ar2,aw,op;
reg [3:0] w,a,b;
wire [3:0] r1,r2,out;
wire c,v,n,z;
always @(negedge clk)
if(ins[9]==1)
begin
ar1=ins[5:3];ar2=3'b000;aw=3'b000;re=1;we=0;ie=1;i=ins[2:0];w=4'b0;
end
else
begin
ar1=ins[5:3];ar2=ins[2:0];aw=3'b000;re=1;we=0;ie=0;i=3'b000;
end
always @(posedge clk)
begin
ar1=3'b000;ar2=3'b000;aw=ins[5:3];re=0;we=1;ie=0;i=3'b000;w=out;
end
registerfile u1(.ar1(ar1),.ar2(ar2),.re(re),.aw(aw),.w(w),.we(we),.clk(clk),.r1(r1),.r2(r2));
alu u2(.a(r1),.b(r2),.op(ins[8:6]),.out(out),.c(c),.n(n),.z(z),.v(v));
endmodule

.........................
module alu(a,b,op,out,c,n,z,v
    );
input [3:0] a,b;
input [2:0] op;
output reg [3:0] out;
output reg z,n,v,c;
reg [2:0] x;
reg c3;
always @*
if (op[2:1]==2'b00)
	begin
		case (op[0])
		1'b0: {c,out}=a+b;
		1'b1: {c,out}=a-b;
		endcase
	{c3,x}={{a[2:0]}-{b[2:0]}};v=c^c3;z = out?1'b0:1'b1;n = {out[3]}?{1'b1}:{1'b0};
	end
else
	begin
		case(op)
		3'b010: out=a&b;
		3'b011: out=a|b;
		3'b100: out=a^b;
		3'b101: out=~a;
		3'b110: out=~(a&b);
		3'b111: out=~(a|b);
		default: out=4'b000;
		endcase
	z = out?{1'b0}:{1'b1};n = {out[3]}?{1'b1}:{1'b0};c=1'bx;v=1'bx;
	end
endmodule
...................
module registerfile(ar1,ar2,aw,re,w,we,clk,r1,r2,ie,i );
	 input re,we,clk;
	 input [2:0] i,ar1,ar2,aw;
	 input [3:0] w;
	 input ie;
	 output reg [3:0] r1,r2;
	 reg [3:0] rf [0:7];
	 reg [3:0] k;
	 initial
	 begin
	 for (k=0;k<8;k=k+1)
	  	 rf[k]=4'b0;
    end
	 always @(posedge clk)
	 if (we==1)
	 begin
	 rf[aw]=w;
	 end
	 always @(negedge clk)
	 
	 if (re==1)
    begin
    r1=rf[ar1];
	 r2 = ie?i:rf[ar2];
	 end
	 else
	 begin
	 r1=4'bx;r2=4'bx;
	 end
endmodule

A FF cannot have more than one clock as input. Therefore when you drive the register at two different clocks (Or even the same clock at 2 different parts of the code) this error will come
 
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