Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

frequency divider output in verilog....

Status
Not open for further replies.
F

FARAH F MIRZA

Newbie level 5
Joined
Apr 4, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
PAKISTAN
Activity points
1,338
this is the code for frequency divider but i am not getting the output wave for divided clock.....
also is there any rule or formula for dividing the frequency from 50mhz to some other value? like how many bits of counter to use ???


Code: 
module clockdivider(clkdivout,reset,clk);
input reset,clk;
output clkdivout;
reg clkdivout;
wire reset,clk;

parameter period=10;
parameter halfperiod=period/2;
reg [3:0]countvalue;



always @(posedge clk)
begin

if(reset)
begin
countvalue = 0;
clkdivout <= 0;
end
else
begin
if(countvalue == period-1)
begin
countvalue = 0;
clkdivout <= 0;
end
else
countvalue = countvalue+1;
if(countvalue == halfperiod)
clkdivout <= 1;
end
end
endmodule
 
Last edited by a moderator:

FARAH F MIRZA said:
this is the code for frequency divider but i am not getting the output wave for divided clock.....
also is there any rule or formula for dividing the frequency from 50mhz to some other value? like how many bits of counter to use ???


module clockdivider(clkdivout,reset,clk);
input reset,clk;
output clkdivout;
reg clkdivout;
wire reset,clk;

parameter period=10;
parameter halfperiod=period/2;
reg [3:0]countvalue;



always @(posedge clk)
begin

if(reset)
begin
countvalue = 0;
clkdivout <= 0;
end
else
begin
if(countvalue == period-1)
begin
countvalue = 0;
clkdivout <= 0;
end
else
countvalue = countvalue+1;
if(countvalue == halfperiod)
clkdivout <= 1;
end
end
endmodule
Click to expand...

Try to replace
if(countvalue == halfperiod)
with
if(countvalue >= halfperiod)

- Deni
 

Deni said:
Try to replace
if(countvalue == halfperiod)
with
if(countvalue >= halfperiod)

- Deni
Click to expand...


PLZ can u tell how to force a clock signal to clk in simulation in modelsim 5.7... there is no option of force here....how will i check the simulation results?

---------- Post added at 13:04 ---------- Previous post was at 12:57 ----------

@deni i have changed the lines and given clock signal from forever command but i am not getting the ouput, both the clkdivout and countervalue are going x
 

No problems with your design. Why do you think it's not working? How did you test it?

Using a divided ("ripple") clock may be inappropriate in a synchronous design. But that's a different topic, I think.

P.S.: I don't see a problem of forcing a clock signal. You need to write a testbench that supplies the clock signal. Study respective Modelsim tutorials.
 

I tested it on isim in xilinx, there there is an option to force clock for simulations
 

I just wrote a simple testbench.

Code: 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:00:38 03/17/2012 
// Design Name: 
// Module Name:    test2_tb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test2_tb();

    reg clk;
	 reg reset;
	 
	 wire clkdivout;
	 
	 initial
	      begin
	          clk<=0;
	          reset<=0;
		 #100 reset <= 1;
		 #100 reset <= 0;
		 #100000 $finish;
	     end
			
	 always #10 clk = ~clk;
			
	 clockdivider clockdivider_module(.clkdivout(clkdivout),.reset(reset),.clk(clk));

endmodule

u can find the result in the image file below.

It proves that your code is right
So what you have to do next is to learn how to write a testbench for your every verilog project.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top