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The drawback for increasing gate area of input tr. in opamp?

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Hughes

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In the CMOS op amp design, the input-refered noise and input offset are related to the gate area of input transistors. To achieve low noise and low offset, input transistors may have to be large in size. But what drawbacks will arise with large input transistors besides the increased chip area?
 

Re: The drawback for increasing gate area of input tr. in op

The drawback will be that your capacitances, gate-drain & drain-bulk, will increase therefore degrading/limiting bandwidth.
 

What other problems may exists if the bandwidth and chip area sufficiently meet the requirements?

I ask this question because someone suggested that I should reduce the input transistors' area in one of my op amp designs. This design was noisy but had a sufficient bandwidth and acceptable chip area.
 

Re: The drawback for increasing gate area of input tr. in op

I don't know what you mean by "noisy." If it's input referred noise, then reducing the gate resistance from increasing the sizing of the transistors is probably the best thing.

The only other drawback I can think of is that your input capacitance will increase because Cgd & Cgs capacitance is increasing. If someone is driving the input with a very high slew rate, this will cause an over/undershoot at the input which will then be amplified by your opamp. The output may then have ringing on the waveform with a high settling time.
 

Thanks.

Yes, I mean the op amp has a large input-refered noise.
 

Re: The drawback for increasing gate area of input tr. in op

Besides the issues mentioned above by the other people, you may also beware of the increase of output swing which may cause the second stage distortion and linearity problem.

Just my ideas. Please correct me if I am wrong.

regards,
jordan76
 

Re: The drawback for increasing gate area of input tr. in op

One other thing also comes to mind. Usually and especially for reducing offset you need to increase W/L, not just WL. For a fixed current, increasing W/L beyond a certain limit will put your diff-pair transistors in subthreshold region of operation, usually not a good thing to do.
 

Re: The drawback for increasing gate area of input tr. in op

One implication of the increase of the input capacitance is that it will prevent the use of large value feedback resistors as it will add phase shift to the feedback, decreasing the phase margin. Decreasing the feedback resistors value to decrease the phase shift will increase the output power delivered to the feedback network and increase the total power consumption of the OpAmp.
 

Re: The drawback for increasing gate area of input tr. in op

sutapanaki said:
One other thing also comes to mind. Usually and especially for reducing offset you need to increase W/L, not just WL. For a fixed current, increasing W/L beyond a certain limit will put your diff-pair transistors in subthreshold region of operation, usually not a good thing to do.
Click to expand...

sutapanaki,
Could you explain more on "For a fixed current, increasing W/L beyond a certain limit will put your diff-pair transistors in subthreshold region of operation" ? Thanks.

regards,
jordan76
 

Re: The drawback for increasing gate area of input tr. in op

If you keep the drain current fixed, given by the tail current source of the diff. pair, and at the same time increase the W/L, you'll get high gm, which is good for reducing offset and noise. But this also reduces the overdrive voltage. Small overdrive voltage means that the difference between Vgs and Vth becomes smaller, that is the transistor starts working with Vgs close to threshold which is close to or in saturation. For one thing, you don't have good matching there anymore.
 

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