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problem with VHDL fsm

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shaiko

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Code:
asynchronous_fsm : process 
begin

  if reset = '0' then 
     dsp_on <= '0' ; 
     general_register <= ( others => "00000001" ) ;	 	 	
     mask_register <= ( others => '0' ) ;	
     event_register <= ( others => '0' ) ;		
     fsm_state <= fsm_idle_state_0 ;

  else

     case state is
		
        when idle_state =>
						
	if event_detected = '1' then
	   event_register <= events ;
	   if unmasked_event_detected = '1' then
	     state <= on_state ;	
	     dsp_on <= '1' ;
	   end if ;	
	end if ;		
				
       when on_state =>
			
           if general_register_1 ( 0 ) = '0' then 	-- has been changed later 					
              dsp_on <= '0' ;	
              state <= idle_state ;	
           end if ;
						
           if address = mask_register then 
	 mask_register <= data ;						
           elsif address = general_register_1_address then
	     general_register_1 <= data ;
           elsif address = general_register_2_address then
	    general_register_2 <= data ;					
           end if ;						
				
       end case ;
		
   end if ;
	
end process asynchronous_fsm ;


I synthesized the code above for an asynchronous FSM and encountered a problem.
When the "event" signal turned to '1' , the fsm would change from "idle_state" to "on_state" but immideatly switch back to "idle_state".

I changed this section of the code that handles the return to idle state condition from on_state:

Code:
if general_register_1 ( 0 ) = '0' then 						
   dsp_on <= '0' ;	
   state <= idle_state ;	
end if ;

to this :

Code:
if general_register_1 ( 0 ) = '0' then 						
   dsp_on <= '0' ;	
   state <= idle_state ;	
else
   dsp_on <= '1' ;	
end if ;

After this change everything worked fine.
Please help me understand why...
 
Last edited:

maybe the general_register_1 has something to do with dsp_on being '0';

Welcome to the ****** world of async design
 
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    shaiko

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Welcome to the ****** world of async design
The example gives a first impressions of possible dead ends in asynchronous design. The behavioral description can lead you to believe in a code functionality that isn't synthesizable at all. Thinking of synthesized hardware, which has been suggested a thousand times to software guys starting HDL is essential particularly in asynchronous design.

- are the latches representing the state information basically able to hold their state under all conditions
- do they still work in presence of glitches that have to be expected for logic elements with simultaneously changing inputs
 
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    shaiko

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There's nothing that I want more than an oscilator on that green board...but it isn't going to happen.
With the constaint of keeping the design asynchronous - any idea on how to make it more reliable ?
 

There's nothing that I want more than an oscilator on that green board...but it isn't going to happen.
With the constaint of keeping the design asynchronous - any idea on how to make it more reliable ?

I'm assuming that the real constraint is that the board design is fixed and not changable at this point, rather than just that you can't add an oscillator for whatever reason. On the slim chance though that you can't add an oscillator but other board changes might be OK, is it possible to add a delay line to the board? If so, then you can construct your own oscillator using your FPGA logic, it could be stopped and started at will. What this would do is to greatly simplify the logic that needs to be designed without a clock, the more complicated stuff could be designed synchronously.

The only part of the design that would need to be run without a clock is logic that starts up the clock at the appropriate time, and then stops it once the clocked part is done.

Kevin Jennings
 
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    shaiko

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I thought about this option.
Unfortunately, zero changes are allowed in the PCB.
 

It should be possible to create a ring oscillator using internal logic only, but I don't know which FPGA's can drive a clock net from a logic output.
 

Many FPGA's also have an interal "configuration" oscillator. If you lok at the design primitives (eg, "libraries for HDL" for xilinx), you might be able to find one. Likewise, a ring oscillator could be constructed. This is a low-quality solution (eg, you could get a wide variation in the frequency generated.)
 

A configuartion oscillator, if accessible by the logic fabric is affected by similar PVT variation as a ring oscillator build from logic cell. You can expect about factor 1:2.

I found a typical delay per logic cell of about 0.4 ns in Cyclone III delay chains. Synthesis attributes or low level primitives are required to make the synthesis tool implement delay chains without optimizing the delay away.
 

Possibly a glitch in latch of signal "general_register_1". But can you tell how often this happens?, is it always returning to IDLE?..

Also, I wonder why use asy.desgn for FSM and wonder why no provision for oscillator i\p(Atleast for future Exp). Maybe you can gate to save power\so.

---------- Post added at 13:54 ---------- Previous post was at 13:46 ----------

Many FPGA's also have an interal "configuration" oscillator. If you lok at the design primitives (eg, "libraries for HDL" for xilinx), you might be able to find one. Likewise, a ring oscillator could be constructed. This is a low-quality solution (eg, you could get a wide variation in the frequency generated.)

Sounds quite new. How could the FPGA device generate it's own clock without a feed clock?. I've never heard of such FPGA's before!!!
 

Sounds quite new. How could the FPGA device generate it's own clock without a feed clock?. I've never heard of such FPGA's before!!!
It's true, though. All FPGAs that support an "active" configuration scheme, reading the configuration from an industry standard serial or parallel flash have it. This applies to all recent Altera FPGAs (Cyclone, Arria, Stratix) and also to Xilinx, I suppose. But the configuration oscillator (a kind of RC- or ring oscillator) isn't neccessarily accessible in the logic. I know, that it's available with Altera MAX II and V series, a small FPGA series with internal flash.
 

A configuartion oscillator, if accessible by the logic fabric is affected by similar PVT variation as a ring oscillator build from logic cell. You can expect about factor 1:2.

I found a typical delay per logic cell of about 0.4 ns in Cyclone III delay chains. Synthesis attributes or low level primitives are required to make the synthesis tool implement delay chains without optimizing the delay away.

If this clock signal is only used to clock the FSM, I'm not sure what would be the problem.
Could you elaborate FvM?

Thx
 

I'm not aware of reporting a particular problem in my post.

PVT is just a fact to consider, the other comments are referring to implementation details.
 

FvM, I'm not saying there are problems.

I know that PVT is just something to concider, that's my point.
If the clock signal (generated by means of the internal osc. or ring osc.) is only used to clock the FSM, I don't think the outside world will suffer from the 'instability' of this clock.

What do you think?
 

Yes, I absolutely agree. The internal oscillator solution is a serious option.
 

Ring oscillator isn't an option - The PCB cannot be changed.
The only option is the internaly generated clock.

Any idea how to implement it on an Actel Igloo FPGA ?
 

Could someone tell me if such internal clock oscillator is available in Xilinx series devices?....
 

it costed me about 2minutes to find out that this internal oscillator is available in Spartan and Virtex devices.
So yes.
 
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    xtcx

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