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Moore and Mealy design in verilog

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ss_engg

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i need verilog code of moore and mealy fsm machine.. if there some one who help out?
 

always @(in or state)
case (state)
`zero:
// last input was a zero
begin
if (in) next_state = `one1;
else next_state = `zero;
end
`one1:
// we've seen one 1
begin
if (in) next_state = `two1s;
else next_state = `zero;
end
`two1s:
// we've seen at least 2 ones
begin
if (in) next_state = `two1s;
else next_state = `zero;
end
endcase
can you please tell me how this always block work of Moore code.?
 

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