Gerry_robotics
Member level 1
Hey Folks,
I'm having a rough time with my VHDL, I get so many errors all the time it's discouraging.
I like doing it but man, it's slow going.
Now my VHDL State machine isn't working.
I have to use case statements for this part of my LAB.
I'm trying to have a series of output ports go HIGH for a certain counter state.
So I have my Address Counter Lines coming in from another VHDL block of code,
this comes in on a Vector input port and then I have CASE statements determining
the output states of my output ports, based on the current Counter decimal value.
The problem is, for all 8 of my State machine states (S0 to S7) I'm getting the following errors:
I've made a COMMENT in my Code to indicate LINE 71.
Here is my current code:
I tried to add this code at the end, but realized that is only when you are not using all of the available states.
So this didn't work either.
Can anyone shed some light as to the cause of this ERROR. My Brain hurts.
Some help here would be nice.
Thanks
-Gerry
I'm having a rough time with my VHDL, I get so many errors all the time it's discouraging.
I like doing it but man, it's slow going.
Now my VHDL State machine isn't working.
I have to use case statements for this part of my LAB.
I'm trying to have a series of output ports go HIGH for a certain counter state.
So I have my Address Counter Lines coming in from another VHDL block of code,
this comes in on a Vector input port and then I have CASE statements determining
the output states of my output ports, based on the current Counter decimal value.
The problem is, for all 8 of my State machine states (S0 to S7) I'm getting the following errors:
Line 71: ERROR, State 'S0' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S1' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S2' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S3' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S4' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S5' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S6' of FSM state variable 'SIG_state' is unreachable.
Line 71: ERROR, State 'S7' of FSM state variable 'SIG_state' is unreachable.
I've made a COMMENT in my Code to indicate LINE 71.
Here is my current code:
Code:
--
-- VHDL Architecture LAB_02_lib.HORZ_DEC_nty.HORZ_DEC_arch
--
-- Created:
-- by - Gerry.UNKNOWN (VIDEO)
-- at - 14:27:12 03/ 1/2012
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY HORZ_DEC_nty IS
PORT(
clk_25Mhz : IN std_logic;
Char_Addr_Lines : IN std_logic_vector(9 downto 0); -- This is essentially just our counter "IMPUT" Bus for this Decoder Block. (The Previous BLock simply controls it to reset at 800)
State_639 : OUT std_logic;
State_659 : OUT std_logic;
State_000 : OUT std_logic;
State_755 : OUT std_logic;
State_640 : OUT std_logic;
State_799 : OUT std_logic;
State_658 : OUT std_logic;
State_756 : OUT std_logic;
Horz_sync_freq : OUT std_logic);
END HORZ_DEC_nty ;
ARCHITECTURE HORZ_DEC_arch OF HORZ_DEC_nty IS
SIGNAL SIG_horz_freq : std_logic;
SIGNAL SIG_h_count : std_logic_vector(9 DOWNTO 0);
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
SIGNAL SIG_state: STATE_TYPE;
BEGIN
------------------------- Horizontal Sync Frequency -----------------------------------
------------------------------- GENERATOR ---------------------------------------------
PROCESS (clk_25Mhz)
BEGIN
IF clk_25Mhz'EVENT AND clk_25Mhz = '1' THEN
IF (SIG_h_count <= 755) AND (SIG_h_count >= 659) THEN
SIG_horz_freq <= '0';
ELSE
SIG_horz_freq <= '1';
END IF;
END IF;
END PROCESS;
---------------------------------------------------------------------------------------
------------------------------ STATE SIGNALS ------------------------------------------
---------------------------------------------------------------------------------------
PROCESS (clk_25Mhz)
BEGIN
IF clk_25Mhz'EVENT AND clk_25Mhz = '1' THEN
CASE SIG_state IS -- -- -- -- -- -- --<<<<<<<<<<<<<<< THIS IS LINE 71
WHEN S0 => -- WHEN in S0 - STATE 639 is Logic HIGH
IF (SIG_h_count <= 639) THEN
State_639 <= '1';
ELSE
State_639 <= '0';
SIG_state <= S1;
END IF;
WHEN S1 => -- WHEN in S1 - STATE 659 is Logic HIGH
IF (SIG_h_count <= 659) THEN
State_659 <= '1';
ELSE
State_659 <= '0';
SIG_state <= S2;
END IF;
WHEN S2 => -- WHEN in S2 - STATE 000 is Logic HIGH
IF (SIG_h_count = 000) THEN
State_000 <= '1';
ELSE
State_000 <= '0';
SIG_state <= S3;
END IF;
WHEN S3 => -- WHEN in S3 - STATE 755 is Logic HIGH
IF (SIG_h_count = 755) THEN
State_755 <= '1';
ELSE
State_755 <= '0';
SIG_state <= S4;
END IF;
WHEN S4 => -- WHEN in S4 - STATE 640 is Logic HIGH
IF (SIG_h_count = 640) THEN
State_640 <= '1';
ELSE
State_640 <= '0';
SIG_state <= S5;
END IF;
WHEN S5 => -- WHEN in S5 - STATE 799 is Logic HIGH
IF (SIG_h_count = 799) THEN
State_799 <= '1';
ELSE
State_799 <= '0';
SIG_state <= S6;
END IF;
WHEN S6 => -- WHEN in S6 - STATE 658 is Logic HIGH
IF (SIG_h_count = 658) THEN
State_658 <= '1';
ELSE
State_658 <= '0';
SIG_state <= S7;
END IF;
WHEN S7 => -- WHEN in S7 - STATE 756 is Logic HIGH
IF (SIG_h_count = 756) THEN
State_756 <= '1';
ELSE
State_756 <= '0';
SIG_state <= S0;
END IF;
END CASE;
END IF;
END PROCESS;
Horz_sync_freq <= SIG_horz_freq;
SIG_h_count <= Char_Addr_Lines;
END ARCHITECTURE HORZ_DEC_arch;
I tried to add this code at the end, but realized that is only when you are not using all of the available states.
WHEN OTHERS =>
SIG_state <= S0
So this didn't work either.
Can anyone shed some light as to the cause of this ERROR. My Brain hurts.
Some help here would be nice.
Thanks
-Gerry