A question about Clock setting in Synthesis

In a chip, we usually use more than one clock. I set false path from one clock to other clocks in the past. Now i doubt the setting is not appropriatly because that we all know set false path in synthesis is not a good setting. Maybe i can set disable timing from one clock to other clock.
Who can tell me which setting is more appropriatly?
This is my setting before:
set _all_clks [all_clocks];
foreach_in_collection _clk $_all_clks {
foreach_in_collection _other_clk [remove_from_collection $_all_clks $_clk] {
set_false_path -from $_clk -to $_other_clk;}
Now i want to modify it to this one:
set _all_clks [all_clocks];
foreach_in_collection _clk $_all_clks {
foreach_in_collection _other_clk [remove_from_collection $_all_clks $_clk] {
set_disable_timing -from $_clk -to $_other_clk;}

firstly,to deal with multi-clock domain,you must synchronize signal form one clock domain to others,if you exchang data you must use fifo or handshake protocal.if your rtl take muti-clock problem in mind,your setting false path between clocks is ok.

secondly,set_disable_timing command disable timing arc between clocks,
set_false_path command disable timing arc between clocks,but still tracing
timing arc.

Yes, in my multi-clock domain of my design, i use synchronize circuits to exchange datas from one clock domain to other domain.
But my corporation engineer tell he never set false paths between clocks. I don't know what's his mean. :?

if you use handshake method,sometimes,need to set multi-cycle to some signal,because handshake method may exchange data basing on multi-cycle method,such as handshake method may assume some signal can settle down after two clock cycles

If you've done a good job in handling the exchanges of data between different clock domain, perhaps using an asynchronous fifo for that. Then you can safely set false paths between the asynchronous clocks.