asbelsare
Newbie level 1
I have a Spartan-6 on one board which needs to send data to a Spartan-3E on another board through a short RJ45 cable. I intend to send the following 6 signals on the RJ45:
- 4 data bits
- Clock Signal
- Send data (SD) line which goes low one clock cycle before the data is transferred.
I'm attaching a chipscopepro analyzer diagram of the send circuit which is working fine:
Following is the receiving end VHDL code for observing the inputs on chipscope, but which shows no signals on chipscope.
Could I know what must be possibly going wrong here?
- 4 data bits
- Clock Signal
- Send data (SD) line which goes low one clock cycle before the data is transferred.
I'm attaching a chipscopepro analyzer diagram of the send circuit which is working fine:
Following is the receiving end VHDL code for observing the inputs on chipscope, but which shows no signals on chipscope.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_receive is
PORT (
SD: in STD_LOGIC;
CLK_IN: in STD_LOGIC;
DATA_OUT: out STD_LOGIC_VECTOR(3 downto 0);
DATA_IN: in STD_LOGIC_VECTOR(3 downto 0)
);
end top_receive;
architecture Behavioral of top_receive is
signal SD_int: std_logic;
signal DATA_IN_int: std_logic_vector(3 downto 0);
begin
SD_int <= SD;
DATA_IN_int(3 downto 0) <= DATA_IN(3 downto 0);
DATA_OUT(3 downto 0) <= DATA_IN_int(3 downto 0);
end Behavioral;Could I know what must be possibly going wrong here?
