FPGA internal POR function

We always make sure that on power-up our FSM is at a known state.

-------------------------
process (clk , rst )
if external_global_reset = '1' then
fsm state <= idle ;
elsif....
-------------------------

"global_reset" is a signal with a dedicated input pin to the FPGA.
But, what if we compile our design without connecting "global_reset" to an input pin at the pin assignment stage ?

Will the internal POR circuitry act the same way as "external_global_reset" and make sure that the FSM loads at an idle state ?
In other words , does the synthesis tool "automatically rewrites" our code and "behind the scenes" it's actually :

if external_global_reset = '1' or POR then
fsm state <= idle ;

?

I see it this way: The synthesis tool doesn't need to rewrite the code. POR is a hardwired feature that sets all registers unconditionally to zero on power-on. An asynchronous reset input of each register can optionally perform the same during operation. The result is however the same.

More important than guessing about internal wiring details of FPGA is to realize, that an asynchronous reset can't guarantee a known state of a FSM, if it's not released synchronously with the respective clock. This is due to a certain risk for the reset release to coincide with the clock edge, causing timing violations and possibly a transition to a wrong state. The Altera Quartus software handbook suggests the below logic for a safe reset.



P.S.: A PLL generated internal FPGA clock can be assumed to start-up in a well defined way. If the PLL is reset together with the registers clocked by it, no further reset synchronizing is required.

What about an asynchronous FSM ?

process
begin
case state is
when idle =>
---
when state_1 =>
---
when state_2 =>
---
end process;

What state will it wake up after power up ?
P.S : is the above even the correct way to write an asynchronous FSM ?

Asynchronous logic, including state machines is a specific topic in digital design. There are some resources in the internet promoting the concept. Unfortunately, usual FPGA tools are supporting it in no way. It's effectively impossible to have the reliable operation of an asynchronous state machine checked in timing analysis or to guarantee, that logic glitches don't mixed it up.

Regarding previously discussed reset timing issues: If you can be sure, that the FSM stays in initial state after reset because no trigger for a state transition is present, it can live with an asynchronous reset.

I understand what you're saying about timing analysis and gliches.
but will this code work at all ?
will it wake-up at idle state ?

process
begin
case state is
when idle =>
---
when state_1 =>
---
when state_2 =>
---
end process;

Sorry, but it don't see a state machine code, just a case structure. Thus I can hardly determine if it works. If you put in state transitions, you have to guarantee that they are ending in a stable state each. Furthermore the synthesized logic needs to be checked for possible unexpected transitions due to logic glitches.

If you are targeting Xilinx FPGA and using XST, the fsm_state registers will be initialized to "idle" after configuration is done regardless the encoding for the idle (it doesn't have to be all 0's). In other words, every single FF in your design will have an initialization value matching your HDL. You will still need to think about the issue with asynchronous reset that FvM talked about though.

shaiko said:

We always make sure that on power-up our FSM is at a known state.

-------------------------
process (clk , rst )
if external_global_reset = '1' then
fsm state <= idle ;
elsif....
-------------------------

"global_reset" is a signal with a dedicated input pin to the FPGA.
But, what if we compile our design without connecting "global_reset" to an input pin at the pin assignment stage ?

Will the internal POR circuitry act the same way as "external_global_reset" and make sure that the FSM loads at an idle state ?
In other words , does the synthesis tool "automatically rewrites" our code and "behind the scenes" it's actually :

if external_global_reset = '1' or POR then
fsm state <= idle ;

?

Click to expand...

The available internal (gate level) coding of initial state depends on the hardware capabilities of the respective FPGA family. Some devices (e.g. newer Altera devices) have POR state of registers fixed to '0'. To avoid additional inverters, the synthesis tool enforces an initial state coding of all zero. Recent Xilinx FPGAs have programmable initial state.