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Why is there a need of having 0 cycle setup path?

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jayfcam

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Hi folks,

I have seen few zero cycle ( set_multicycle_path 0) setup paths in design. Can you explain why there is a need of having 0 cycle setup path? what is a advantage of the same? How do we check hold violations for these kind of paths?


Regards,
Jay
 

Re: zero (0) cycle paths

Thanks a lot for the response.

but the link you provided is about FPGA. I want to understand this in ASIC flow.

Thanks
Jay
 

Re: zero (0) cycle paths

Multicycle paths are those paths which use more then one clock cycle . Usually DC/PT check path timing in one cycle.
If you have a path in your design ,which cannot finished operation in one cycle, you can tell DC/PT this path is a multi cycle path.

Hold multicycle constraints are based on the default hold position (the default value is 0). An end hold multicycle constraint of 1 effectively subtracts one destination clock period from the default hold latch edge
 

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