Power estimation of logic design

Hello,

Although this subject is highly discussed everywhere, i couldn't find a decent answer to the questions regarding estimation of VLSI and logic design. By estimation i mean not using EDA tools that perform power analysis or an existing synthesized deign.

I'm referring to the thumb rules estimation of power consumed in different process (90,65, 40, G LP MS etc) of logic (AKA gates) and memories (aka SRAM).

I just want to estimate how much power will my design consume assuming the following:
1- I have an estimation of number of Kgates
2- I have the target frequency that the design will run
3- i have an estimation regarding the activity factor
4- i have the memories and the frequency they will be accessed.

I know that there are some basic rules to roughly calculate the power, i just can't find them.

Let's have a fruitful thread about this important matter.

uzi

Salaam
Your design could be power estimated by general flow:
Simulate your design as the simulator log nets switching activities in a VCD file. Then with your design, standard cell library and the VCD file, you could estimate the power consumption with PrimeTime PX.

The basic rule comes from the previous project for the std cell area/power.
For the memories, we usually used the spec generated by the memories compiler.