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module MatlabConnect(clk, RxD, TxD, GPout, GPin, LEDR);
// Create 8 outputs on the FPGA - GPout is updated by any character that 
// the FPGA receives. Create 8 inputs on the FPGA - GPin is transmitted 
// every time the FPGA receives a character.

input        clk;
input        RxD;
input [7:0] GPin;

output         TxD;
output [7:0] GPout;
output [7:0]  LEDR;

wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver deserializer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));

reg [7:0] GPout;
always @(posedge clk) if(RxD_data_ready) GPout <= RxD_data;

async_transmitter serializer(.clk(clk), .TxD(TxD), .TxD_start(RxD_data_ready), .TxD_data(GPin));

assign LEDR[0] = GPout[0];
assign LEDR[1] = GPout[1];
assign LEDR[2] = GPout[2];
assign LEDR[3] = GPout[3];
assign LEDR[4] = GPout[4];
assign LEDR[5] = GPout[5];
assign LEDR[6] = GPout[6];
assign LEDR[7] = GPout[7];

endmodule

module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready;
output [7:0] RxD_data;

// Set the Clock frequency to 25MHz and the Baud rate to 115200Hz
parameter ClkFrequency = 25000000;
parameter Baud = 115200;

// Detect if a gap occurs in the received stream of characters; useful if
// multiple character are sent in a burst so that multiple characters can 
// be treated as a packet
output RxD_endofpacket;  // One clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle;         // No data is being received

// Baud generator, using 8 times oversampling
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];

// Asynchronous Receiver
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// We invert RxD, so that the idle becomes "0", to prevent a phantom 
// character to be received at startup

reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;

always @(posedge clk)
if(Baud8Tick)
begin
	if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
	else 
	if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;

	if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
	else
	if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end

reg [3:0] state;
reg [3:0] bit_spacing;

// "next_bit" controls when the data sampling occurs depending on how 
// noisy the RxD is, different values might work better with a clean
// connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);

always @(posedge clk)
if(state==0)
	bit_spacing <= 4'b0000;
else
if(Baud8Tick)
	bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};

always @(posedge clk)
if(Baud8Tick)
case(state)
	4'b0000: if(RxD_bit_inv) state <= 4'b1000;  // Start Bit found?
	4'b1000: if(next_bit) state <= 4'b1001;     // Bit 0
	4'b1001: if(next_bit) state <= 4'b1010;     // Bit 1
	4'b1010: if(next_bit) state <= 4'b1011;     // Bit 2
	4'b1011: if(next_bit) state <= 4'b1100;     // Bit 3
	4'b1100: if(next_bit) state <= 4'b1101;     // Bit 4
	4'b1101: if(next_bit) state <= 4'b1110;     // Bit 5
	4'b1110: if(next_bit) state <= 4'b1111;     // Bit 6
	4'b1111: if(next_bit) state <= 4'b0001;     // Bit 7
	4'b0001: if(next_bit) state <= 4'b0000;     // Stop Bit
	default: state <= 4'b0000;
endcase

reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};

reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
	RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv);  // Ready only if the Stop Bit is received
	RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 &&  RxD_bit_inv);  // Error if the Stop Bit is not received
end

reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);

endmodule

module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;

// Set the Clock frequency to 25MHz and the Baud rate to 115200Hz
// In RegsiterInputData mode, the input doesn't have to stay valid while
// the character is being transmitted
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter RegisterInputData = 1;	

// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef DEBUG
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;
`else
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
`endif

wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

// Asynchronous Transmitter
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;

reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;

always @(posedge clk)
case(state)
	4'b0000: if(TxD_start) state <= 4'b0001;
	4'b0001: if(BaudTick) state <= 4'b0100;
	4'b0100: if(BaudTick) state <= 4'b1000;  // Start
	4'b1000: if(BaudTick) state <= 4'b1001;  // Bit 0
	4'b1001: if(BaudTick) state <= 4'b1010;  // Bit 1
	4'b1010: if(BaudTick) state <= 4'b1011;  // Bit 2
	4'b1011: if(BaudTick) state <= 4'b1100;  // Bit 3
	4'b1100: if(BaudTick) state <= 4'b1101;  // Bit 4
	4'b1101: if(BaudTick) state <= 4'b1110;  // Bit 5
	4'b1110: if(BaudTick) state <= 4'b1111;  // Bit 6
	4'b1111: if(BaudTick) state <= 4'b0010;  // Bit 7
	4'b0010: if(BaudTick) state <= 4'b0011;  // Stop 1
	4'b0011: if(BaudTick) state <= 4'b0000;  // Stop 2
	default: if(BaudTick) state <= 4'b0000;
endcase

// Output mux
reg muxbit;
always @( * )
case(state[2:0])
	3'd0: muxbit <= TxD_dataD[0];
	3'd1: muxbit <= TxD_dataD[1];
	3'd2: muxbit <= TxD_dataD[2];
	3'd3: muxbit <= TxD_dataD[3];
	3'd4: muxbit <= TxD_dataD[4];
	3'd5: muxbit <= TxD_dataD[5];
	3'd6: muxbit <= TxD_dataD[6];
	3'd7: muxbit <= TxD_dataD[7];
endcase

// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit);  // register the output to make it glitch free

endmodule