cysco
Newbie level 5
Someone said that the SDF gate simulation will check the false path is correctly setting in the timing constraint(.pt).
But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So the gate simulation can not check the false path is correct or not?
In fact SDF gate simulation is only the double check of the STA(primetime).
But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So the gate simulation can not check the false path is correct or not?
In fact SDF gate simulation is only the double check of the STA(primetime).
